Intel BX80646I54430, CM8064601466200 manual Digital Display Interface Group DC Specifications

Page 101
Digital Display Interface Group DC Specifications

Electrical Specifications—Processor

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

 

Parameter

Min

Typ

Max

Units

Notes1

 

 

 

 

DDR3/DDR3L Control

 

 

 

 

5, 11,

 

RON_DN(CTL)

 

Buffer pull-down

19

25

31

Ω

 

 

13

 

 

 

 

Resistance

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DDR3/DDR3L Reset

 

 

 

 

 

 

RON_UP(RST)

 

Buffer pull-up

40

80

130

Ω

—

 

 

 

 

Resistance

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DDR3/DDR3L Reset

 

 

 

 

 

 

RON_DN(RST)

 

Buffer pull-up

40

80

130

Ω

—

 

 

 

 

Resistance

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input Leakage Current

 

 

 

 

 

 

 

 

 

(DQ, CK)

 

 

 

 

 

 

ILI

 

 

0V

—

—

0.7

mA

—

 

 

 

 

0.2*VDDQ

 

 

 

 

 

 

 

 

 

0.8*VDDQ

 

 

 

 

 

 

 

 

 

Input Leakage Current

 

 

 

 

 

 

 

 

 

(CMD, CTL)

 

 

 

 

 

 

ILI

 

 

0V

—

—

1.0

mA

—

 

 

 

 

0.2*VDDQ

 

 

 

 

 

 

 

 

 

0.8*VDDQ

 

 

 

 

 

 

SM_RCOMP0

 

Command COMP

99

100

101

Ω

8

 

 

Resistance

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SM_RCOMP1

 

Data COMP Resistance

74.25

75

75.75

Ω

8

 

 

 

 

 

 

 

 

 

 

SM_RCOMP2

 

ODT COMP Resistance

99

100

101

Ω

8

 

 

 

 

 

 

 

 

 

Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

 

 

2.

VIL

is defined as the maximum voltage level at a receiving agent that will be interpreted as a

 

 

logical low value.

 

 

 

 

 

 

3.

VIH

is defined as the minimum voltage level at a receiving agent that will be interpreted as a

 

 

logical high value.

 

 

 

 

 

 

4. VIH and VOH may experience excursions above VDDQ. However, input signal drivers must comply

 

 

with the signal quality specifications.

 

 

 

 

 

 

5. This is the pull up/down driver resistance.

 

 

 

 

 

6. RTERM is the termination on the DIMM and in not controlled by the processor.

 

 

 

7. The minimum and maximum values for these signals are programmable by BIOS to one of the

 

 

two sets.

 

 

 

 

 

 

8. SM_RCOMPx resistance must be provided on the system board with 1% resistors. SM_RCOMPx

 

 

resistors are to VSS.

 

 

 

 

 

 

9. SM_DRAMPWROK rise and fall time must be < 50 ns measured between VDDQ *0.15 and VDDQ

 

 

*0.47.

 

 

 

 

 

 

 

10.SM_VREF is defined as VDDQ/2.

 

 

 

 

 

 

11.Maximum-minimum range is correct; however, center point is subject to change during MRC

 

 

boot training.

 

 

 

 

 

 

12.Processor may be damaged if VIH exceeds the maximum voltage for extended periods.

 

 

13.The MRC during boot training might optimize RON outside the range specified.

 

 

Table 51.

Digital Display Interface Group DC Specifications

 

 

 

 

 

 

 

 

 

 

 

Symbol

Parameter

Min

Typ

Max

Units

 

 

 

 

 

 

 

 

VIL

HPD Input Low Voltage

—

—

0.8

V

 

 

 

 

 

 

 

 

VIH

HPD Input High Voltage

2.25

—

3.6

V

 

 

 

 

 

 

 

 

Vaux(Tx)

Aux peak-to-peak voltage at transmitting

0.39

—

1.38

V

 

device

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Vaux(Rx)

Aux peak-to-peak voltage at receiving

0.32

—

1.36

V

 

device

 

 

 

 

 

 

 

 

 

 

 

 

 

Desktop 4th Generation Intel® Core™ Processor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron® Processor Family

December 2013

Datasheet – Volume 1 of 2

Order No.: 328897-004

101

Page 100 Page 102
Image 101
Page 100 Page 102
Contents December Datasheet - Volume 1 ofDatasheet - Volume 1 of 2 4.0 Power Management ContentsRevision History 1.0 Introduction5.0 Thermal Management 6.0 Signal DescriptionProcessor-Contents 8.0 Package Mechanical Specifications 7.0 Electrical Specifications9.0 Processor Ball and Signal Information 7.8.1 Platform Environment Control Interface PECI DC CharacteristicsFigures Tables-Processor TablesProcessor-Tables Revision History-Processor Revision HistoryProcessor-Introduction 1.0 Introduction1.1 Supported Technologies Figure 1. Platform Block DiagramProcessor Platform Controller Hub PCH1.2 Interfaces 1.3 Power Management SupportProcessor Core System1.5 Package Support 1.4 Thermal Management Support1.6 Terminology Terminologywith Virtual Machine Monitor software, enables multiple, robust independent software Term Related Documents 1.7 Related DocumentsDocument Number / Locationhttp specificationsproducts/processor manuals/index.htm2.1 System Memory Interface 2.0 InterfacesProcessor DIMM Support by Product Supported UDIMM Module Configurations2.1.1 System Memory Technology Supported DDR3 / DDR3L System Memory Timing Support Supported SO-DIMM Module Configurations AIO Only2.1.2 System Memory Timing Support Single-Channel Mode 2.1.3 System Memory Organization ModesDual-Channel Mode - Intel Flex Memory Technology Mode Figure 2. Intel Flex Memory Technology OperationsJust-in-Time Command Scheduling 2.1.3.2 Intel Fast Memory Access Intel FMA Technology EnhancementsCommand Overlap 2.1.3.1 System Memory Frequency2.2 PCI Express* Interface Table 7. PCI Express* Supported Configurations in Desktop Products2.2.1 PCI Express* Support 2.1.3.3 Data Scrambling2.2.2 PCI Express* Architecture 2.2.3 PCI Express* Configuration MechanismPCI Express* Lanes Connection PCI Express* Related Register Structures in the ProcessorPCI Express* Port Figure 4. PCI Express* Typical Operation 16 Lanes Mapping 2.3 Direct Media Interface DMI1 X 4 Controller 1 X 8 ControllerDMI Link Down DMI Error Flow2.5 Processor Graphics Controller GT 2.4 Processor Graphics2.5.1 3D and Video Engines for Graphics Processing Figure 5. Processor Graphics Controller Unit Block Diagram3D Pipeline 3D Engine Execution UnitsGeometry Shader GS Stage Vertex Shader VS StageClip Stage Strips and Fans SF StageLogical 128-Bit Fixed BLT and 256 Fill Engine 2.6 Digital Display Interface DDI2.5.2 Multi Graphics Controllers Multi-Monitor Support Figure 6. Processor Display Architecture Sink Device Source DeviceDisplayPort Figure 7. DisplayPort* OverviewHDMI Sink HDMI SourceFigure 8. HDMI* Overview HDMI Txembedded DisplayPort Multiple Display ConfigurationsIntegrated Audio Table 8. Processor Supported Audio Formats over HDMI*and DisplayPortHigh-bandwidth Digital Content Protection HDCP Valid Three Display Configurations through the Processor2.8.1 PECI Bus Architecture 2.7 Intel Flexible Display Interface Intel FDI2.8 Platform Environmental Control Interface PECI PECI Figure 9. PECI Host-Clients Connection ExampleHost / Originator PECI Client3.1 Intel Virtualization Technology Intel VT 3.0 TechnologiesIntel VT-x Objectives ing=VTIntel VT-x Features Intel VT-d Objectives Figure 10. Device to Domain Mapping Structures Intel VT-d Features3.2 Intel Trusted Execution Technology Intel TXT 3.3 Intel Hyper-Threading Technology Intel HT Technology Intel Turbo Boost Technology 2.0 Frequency 3.4 Intel Turbo Boost Technology3.5 Intel Advanced Vector Extensions 2.0 Intel AVX2 Intel Secure Key 3.6 Intel Advanced Encryption Standard New Instructions Intel AES-NIPCLMULQDQ Instruction 3.8 Intel 64 Architecture x2APIC 3.11 Supervisor Mode Execution Protection SMEP 3.9 Power Aware Interrupt Routing PAIR3.10 Execute Disable Bit Figure 11. Processor Power States 4.0 Power ManagementNote Power states availability may vary between the different SKUs S0 - Processor Fully powered on full on mode / connected standby modeSystem States 4.1 Advanced Configuration and Power Interface ACPI States SupportedProcessor Core / Package State Support Integrated Memory Controller States4.2.1 Enhanced Intel SpeedStep Technology Key Features 4.2 Processor Core Power ManagementDirect Media Interface DMI States G, S, and C Interface State CombinationsFigure 12. Idle Power Management Breakdown of the Processor Cores 4.2.2 Low-Power Idle StatesThread Core 0 StateFigure 13. Thread and Core C-State Entry and Exit 4.2.3 Requesting Low-Power Idle StatesCoordination of Thread Power States at the Core Level Core C0 State 4.2.4 Core C-State RulesCore C1/C1E State Core C3 StateCore C6 State 4.2.5 Package C-StatesCore C7 State C-State Auto-DemotionCoordination of Core Power States at the Package Level Package C1/C1E State Figure 14. Package C-State Entry and ExitPackage C0 State Package C3 State Package C2 StatePackage C6 State Package C7 StateDeepest Package C-State Available 4.2.6 Package C-States and Display Resolutions4.3.1 Disabling Unused System Memory Outputs 4.3 Integrated Memory Controller IMC Power ManagementNo power-down CKE disable 4.3.2 DRAM Power Management and Initialization4.3.2.2 Conditional Self-Refresh 4.3.2.3 Dynamic Power-Down4.3.2.1 Initialization Role of CKE 4.5 Direct Media Interface DMI Power Management 4.4 PCI Express* Power Management4.3.3 DRAM Running Average Power Limitation RAPL 4.3.4 DDR Electrical Power Gating EPG4.6.1 Intel Rapid Memory Power Management Intel RMPM 4.6 Graphics Power Management4.6.2 Graphics Render C-State 4.6.3 Intel Graphics Dynamic FrequencyThermal Management-Processor 5.0 Thermal Management5.1 Desktop Processor Thermal Profiles Desktop Processor Thermal SpecificationsProcessor-Thermal Management ProfileTCASE = 0.33 * Power + 5.1.1 Processor PCG 2013D Thermal ProfileTTV Power W Case5.1.2 Processor PCG 2013C Thermal Profile 5.1.3 Processor PCG 2013B Thermal Profile 5.1.4 Processor PCG 2013A Thermal Profile 5.3 Fan Speed Control Scheme with Digital Thermal Sensor DTS 5.2 Thermal MetrologyMeasure TCASE at the geometric center of the package 37.5 37.5ΨCA = TCASE-MAX - TAMBIENT-TARGET / TDP Figure 20. Digital Thermal Sensor DTS 1.1 Definition Points5.4 Fan Speed Control Scheme with Digital Thermal Sensor DTS Thermal Margin Slope 5.5 Processor TemperatureFigure 21. Digital Thermal Sensor DTS Thermal Profile Definition Frequency Control 5.6 Adaptive Thermal MonitorCritical Temperature Flag Clock ModulationImmediate Transition to Combined TM1 and TM2 PROCHOT# Signal 5.8 Digital Thermal Sensor 5.7 THERMTRIP# Signal5.8.1 Digital Thermal Sensor Accuracy Taccuracy 5.9.1 Intel Turbo Boost Technology Power Control and Reporting5.9 Intel Turbo Boost Technology Thermal Considerations Intel Turbo Boost Technology 2.0 Package Power Control Settings 5.9.2 Package Power Control5.9.3 Turbo Time Parameter Figure 22. Package Power Control6.1 System Memory Interface Signals 6.0 Signal DescriptionSignal Description Buffer Types Memory Channel A SignalsSignal Description-Processor Memory Channel B SignalsMemory Reference and Compensation Signals 6.2 Memory Reference and Compensation SignalsDDR3/DDR3L Reference Voltage This signal is used as System Memory Impedance CompensationReset and Miscellaneous Signals 6.3 Reset and Miscellaneous SignalsCFG3 MSR Privacy Bit Feature CFG65 PCI Express* Bifurcation6.5 Display Interface Signals 6.4 PCI Express*-Based Interface SignalsPCI Express* Graphics Interface Signals Display Interface Signals6.8 Testability Signals 6.7 Phase Locked Loop PLL SignalsPhase Locked Loop PLL Signals Testability Signals6.10 Power Sequencing Signals 6.9 Error and Thermal Protection SignalsError and Thermal Protection Signals Power Sequencing Signals6.12 Sense Signals 6.11 Processor Power Signals6.13 Ground and Non-Critical to Function NCTF Signals Processor Power Signals7.2 Power and Ground Lands 7.0 Electrical Specifications7.1 Integrated Voltage Regulator 7.3 VCC Voltage Identification VIDElectrical Specifications-Processor Table 45. Voltage Regulator VR 12.5 Voltage Identificationcontinued Processor-Electrical Specificationscontinued continued Electrical Specifications-Processorcontinued continued Signal Groups 7.4 Reserved or Unused Signals7.5 Signal Groups DDR3 / DDR3L Reference Voltage Signals DDR3 / DDR3L Data SignalsPower / Ground / Other DDR3 / DDR3L Compensation7.7 DC Specifications 7.6 Test Access Port TAP ConnectionPCI Express* Graphics Digital Media Interface DMI7.8 Voltage and Current Specifications Electrical Specifications-Processor VCCIOOUT, VCOMPOUT, and VCCIOTERM DDR3 / DDR3L Signal Group DC SpecificationsDigital Display Interface Group DC Specifications GTL Signal Group and Open Drain Signal Group DC Specifications embedded DisplayPort* eDP* Group DC SpecificationsCMOS Signal Group DC Specifications PCI Express* DC Specifications 7.8.1 Platform Environment Control Interface PECI DC CharacteristicsFigure 23. Input Device Hysteresis 7.8.2 Input Device Hysteresis8.2 Package Loading Specifications 8.0 Package Mechanical SpecificationsFigure 24. Processor Package Assembly Sketch 8.1 Processor Component Keep-Out Zone8.5 Processor Mass Specification 8.4 Package Insertion SpecificationsProcessor Loading Specifications 8.3 Package Handling Guidelines8.8 Processor Land Coordinates 8.7 Processor MarkingsProcessor Materials Figure 25. Processor Top-Side MarkingsFigure 26. Processor Package Land Coordinates 8.9 Processor Storage SpecificationsProcessor Storage Specifications TIMEsustained storage RHsustained storageProcessor Ball List by Signal Name 9.0 Processor Ball and Signal InformationProcessor Ball and Signal Information-Processor Processor-Processor Ball and Signal Information Signal Name Signal NameSignal Name Ball #Signal Name Signal NameSignal Name Ball #Signal Name AU20 Signal Name Signal NameSignal Name Ball #Signal Name Signal NameSignal Name Ball #Signal Name Signal NameSignal Name Ball #Signal Name Signal NameSignal Name Ball #
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BX80633I74960X, BX80646I34130, BX80646I54430, BX80646I74770K, BX80646I74770 specifications

The Intel CM8063701159502, or BX80637I53470, is a powerful CPU designed for modern computing needs. This processor belongs to Intel's 4th generation of Core i5 processors, commonly known as "Haswell". It showcases Intel's commitment to enhancing performance, increasing energy efficiency, and delivering an enriching user experience.

One of the main features of the Intel Core i5-3470 is its quad-core architecture. This allows the processor to handle multiple threads simultaneously, making it adept at multitasking and running demanding applications efficiently. With a base clock speed of 3.2 GHz, it can boost up to 3.6 GHz using Intel’s Turbo Boost technology, providing additional power when needed for intensive tasks like gaming or video editing.

The Intel i5-3470 features Intel's HD Graphics 2500, which offers decent graphics performance for everyday tasks and casual gaming. This integrated graphics solution is capable of delivering high-definition visuals and supports DirectX 11, making it suitable for lightweight gaming experiences without the need for an additional dedicated graphics card.

Another standout characteristic of the BX80637I53470 is its support for Intel Smart Cache, which is an advanced caching technology. It provides a shared cache pool that enhances performance by reducing the time it takes to access frequently used data. This feature, coupled with Intel's instruction set architecture, allows for improved processing agility and efficiency across applications.

The processor is built on a 22nm manufacturing process, which results in reduced power consumption and heat generation compared to its predecessors. It has a thermal design power (TDP) of 77 watts, making it energy efficient while still delivering robust performance. Additionally, the Core i5-3470 supports DDR3 memory, with speeds up to 1600 MHz, enabling quick data retrieval and improved system responsiveness.

Security is another important aspect of the Intel i5-3470, featuring Intel Secure Key and Intel AES New Instructions (AES-NI), which protect sensitive data and enhance encryption performance.

In conclusion, the Intel CM8063701159502, or BX80637I53470, encapsulates modern computing technology with its powerful quad-core performance, integrated graphics, energy efficiency, and robust security features, making it a versatile choice for a wide range of computing tasks. Whether users are engaging in casual gaming, productivity tasks, or multimedia consumption, this processor demonstrates a solid balance of performance and efficiency, providing an excellent computing experience overall.
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