Intel BXF80646I74770K manual Memory Channel B Signals, Signal Description-Processor, continued

Page 83
Signal Description—Processor

Signal Description—Processor

 

 

 

 

 

 

 

 

 

Signal Name

Description

Direction / Buffer

 

 

 

 

Type

 

 

 

 

 

 

SA_RAS#

RAS Control Signal: This signal is used with SA_CAS# and

O

 

SA_WE# (along with SA_CS#) to define the SRAM Commands.

DDR3/DDR3L

 

 

 

 

 

 

 

 

SA_CAS#

CAS Control Signal: This signal is used with SA_RAS# and

O

 

SA_WE# (along with SA_CS#) to define the SRAM Commands.

DDR3/DDR3L

 

 

 

 

 

 

 

 

 

Data Strobes: SA_DQS[8:0] and its complement signal group

I/O

 

SA_DQS[8:0]

make up a differential strobe pair. The data is captured at the

 

SA_DQSN[8:0]

crossing point of SA_DQS[8:0] and SA_DQS#[8:0] during read

DDR3/DDR3L

 

 

and write transactions.

 

 

 

 

 

 

 

SA_DQ[63:0]

Data Bus: Channel A data signal interface to the SDRAM data

I/O

 

bus.

DDR3/DDR3L

 

 

 

 

 

 

 

 

SA_MA[15:0]

Memory Address: These signals are used to provide the

O

 

multiplexed row and column address to the SDRAM.

DDR3/DDR3L

 

 

 

 

 

 

 

 

 

SDRAM Differential Clock: These signals are Channel A

 

 

 

SDRAM Differential clock signal pairs. The crossing of the

O

 

SA_CK[3:0]

positive edge of SA_CK and the negative edge of its complement

 

DDR3/DDR3L

 

 

SA_CK# are used to sample the command and control signals on

 

 

 

 

 

the SDRAM.

 

 

 

 

 

 

 

 

Clock Enable: (1 per rank). These signals are used to:

 

 

SA_CKE[3:0]

• Initialize the SDRAMs during power-up

O

 

• Power-down SDRAM ranks

DDR3/DDR3L

 

 

 

 

• Place all SDRAM ranks into and out of self-refresh during STR

 

 

 

 

 

 

 

 

Chip Select: (1 per rank). These signals are used to select

O

 

SA_CS#[3:0]

particular SDRAM components during the active state. There is

 

DDR3/DDR3L

 

 

one Chip Select for each SDRAM rank.

 

 

 

 

 

 

 

 

 

SA_ODT[3:0]

On Die Termination: Active Termination Control.

O

 

 

 

DDR3/DDR3L

 

 

 

 

 

 

 

 

 

Table 31.

Memory Channel B Signals

 

 

 

 

 

 

 

Signal Name

Description

 

Direction / Buffer

 

 

 

 

Type

 

 

 

 

 

 

SB_BS[2:0]

Bank Select: These signals define which banks are selected

 

O

 

within each SDRAM rank.

 

DDR3/DDR3L

 

 

 

 

 

 

 

 

 

 

Write Enable Control Signal: This signal is used with

 

O

 

SB_WE#

SB_RAS# and SB_CAS# (along with SB_CS#) to define the

 

 

 

DDR3/DDR3L

 

 

SDRAM Commands.

 

 

 

 

 

 

 

 

 

 

 

SB_RAS#

RAS Control Signal: This signal is used with SB_CAS# and

 

O

 

SB_WE# (along with SB_CS#) to define the SRAM Commands.

 

DDR3/DDR3L

 

 

 

 

 

 

 

 

 

SB_CAS#

CAS Control Signal: This signal is used with SB_RAS# and

 

O

 

SB_WE# (along with SB_CS#) to define the SRAM Commands.

 

DDR3/DDR3L

 

 

 

 

 

 

 

 

 

 

Data Strobes: SB_DQS[8:0] and its complement signal group

 

I/O

 

SB_DQS[8:0]

make up a differential strobe pair. The data is captured at the

 

 

SB_DQSN[8:0]

crossing point of SB_DQS[8:0] and its SB_DQS#[8:0] during

 

DDR3/DDR3L

 

 

read and write transactions.

 

 

 

 

 

 

 

 

SB_DQ[63:0]

Data Bus: Channel B data signal interface to the SDRAM data

 

I/O

 

bus.

 

DDR3/DDR3L

 

 

 

 

 

 

 

 

 

SB_MA[15:0]

Memory Address: These signals are used to provide the

 

O

 

multiplexed row and column address to the SDRAM.

 

DDR3/DDR3L

 

 

 

 

 

 

 

 

 

 

 

 

continued...

Desktop 4th Generation Intel® Core™ Processor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron® Processor Family

December 2013

Datasheet – Volume 1 of 2

Order No.: 328897-004

83

Page 82 Page 84
Image 83
Page 82 Page 84
Contents December Datasheet - Volume 1 ofDatasheet - Volume 1 of 2 1.0 Introduction Contents4.0 Power Management Revision History5.0 Thermal Management 6.0 Signal DescriptionProcessor-Contents 7.8.1 Platform Environment Control Interface PECI DC Characteristics 7.0 Electrical Specifications8.0 Package Mechanical Specifications 9.0 Processor Ball and Signal InformationFigures Tables-Processor TablesProcessor-Tables Revision History-Processor Revision HistoryProcessor-Introduction 1.0 IntroductionPlatform Controller Hub PCH Figure 1. Platform Block Diagram1.1 Supported Technologies ProcessorSystem 1.3 Power Management Support1.2 Interfaces Processor CoreTerminology 1.4 Thermal Management Support1.5 Package Support 1.6 Terminologywith Virtual Machine Monitor software, enables multiple, robust independent software continued Number / Location 1.7 Related DocumentsRelated Documents Documentmanuals/index.htm specificationshttp products/processor2.1 System Memory Interface 2.0 InterfacesProcessor DIMM Support by Product Supported UDIMM Module Configurations2.1.1 System Memory Technology Supported DDR3 / DDR3L System Memory Timing Support Supported SO-DIMM Module Configurations AIO Only2.1.2 System Memory Timing Support Figure 2. Intel Flex Memory Technology Operations 2.1.3 System Memory Organization ModesSingle-Channel Mode Dual-Channel Mode - Intel Flex Memory Technology Mode2.1.3.1 System Memory Frequency 2.1.3.2 Intel Fast Memory Access Intel FMA Technology EnhancementsJust-in-Time Command Scheduling Command Overlap2.1.3.3 Data Scrambling Table 7. PCI Express* Supported Configurations in Desktop Products2.2 PCI Express* Interface 2.2.1 PCI Express* Support2.2.2 PCI Express* Architecture 2.2.3 PCI Express* Configuration MechanismPCI Express* Lanes Connection PCI Express* Related Register Structures in the ProcessorPCI Express* Port 1 X 8 Controller 2.3 Direct Media Interface DMIFigure 4. PCI Express* Typical Operation 16 Lanes Mapping 1 X 4 ControllerDMI Link Down DMI Error Flow2.5 Processor Graphics Controller GT 2.4 Processor Graphics3D Engine Execution Units Figure 5. Processor Graphics Controller Unit Block Diagram2.5.1 3D and Video Engines for Graphics Processing 3D PipelineStrips and Fans SF Stage Vertex Shader VS StageGeometry Shader GS Stage Clip StageLogical 128-Bit Fixed BLT and 256 Fill Engine 2.6 Digital Display Interface DDI2.5.2 Multi Graphics Controllers Multi-Monitor Support Figure 6. Processor Display Architecture Figure 7. DisplayPort* Overview Source DeviceSink Device DisplayPortHDMI Tx HDMI SourceHDMI Sink Figure 8. HDMI* OverviewTable 8. Processor Supported Audio Formats over HDMI*and DisplayPort Multiple Display Configurationsembedded DisplayPort Integrated AudioHigh-bandwidth Digital Content Protection HDCP Valid Three Display Configurations through the Processor2.8.1 PECI Bus Architecture 2.7 Intel Flexible Display Interface Intel FDI2.8 Platform Environmental Control Interface PECI PECI Client Figure 9. PECI Host-Clients Connection ExamplePECI Host / Originatoring=VT 3.0 Technologies3.1 Intel Virtualization Technology Intel VT Intel VT-x ObjectivesIntel VT-x Features Intel VT-d Objectives Figure 10. Device to Domain Mapping Structures Intel VT-d Features3.2 Intel Trusted Execution Technology Intel TXT 3.3 Intel Hyper-Threading Technology Intel HT Technology Intel Turbo Boost Technology 2.0 Frequency 3.4 Intel Turbo Boost Technology3.5 Intel Advanced Vector Extensions 2.0 Intel AVX2 Intel Secure Key 3.6 Intel Advanced Encryption Standard New Instructions Intel AES-NIPCLMULQDQ Instruction 3.8 Intel 64 Architecture x2APIC 3.11 Supervisor Mode Execution Protection SMEP 3.9 Power Aware Interrupt Routing PAIR3.10 Execute Disable Bit S0 - Processor Fully powered on full on mode / connected standby mode 4.0 Power ManagementFigure 11. Processor Power States Note Power states availability may vary between the different SKUsIntegrated Memory Controller States 4.1 Advanced Configuration and Power Interface ACPI States SupportedSystem States Processor Core / Package State SupportG, S, and C Interface State Combinations 4.2 Processor Core Power Management4.2.1 Enhanced Intel SpeedStep Technology Key Features Direct Media Interface DMI StatesCore 0 State 4.2.2 Low-Power Idle StatesFigure 12. Idle Power Management Breakdown of the Processor Cores ThreadFigure 13. Thread and Core C-State Entry and Exit 4.2.3 Requesting Low-Power Idle StatesCoordination of Thread Power States at the Core Level Core C3 State 4.2.4 Core C-State RulesCore C0 State Core C1/C1E StateC-State Auto-Demotion 4.2.5 Package C-StatesCore C6 State Core C7 StateCoordination of Core Power States at the Package Level Package C1/C1E State Figure 14. Package C-State Entry and ExitPackage C0 State Package C7 State Package C2 StatePackage C3 State Package C6 StateDeepest Package C-State Available 4.2.6 Package C-States and Display Resolutions4.3.1 Disabling Unused System Memory Outputs 4.3 Integrated Memory Controller IMC Power ManagementNo power-down CKE disable 4.3.2 DRAM Power Management and Initialization4.3.2.2 Conditional Self-Refresh 4.3.2.3 Dynamic Power-Down4.3.2.1 Initialization Role of CKE 4.3.4 DDR Electrical Power Gating EPG 4.4 PCI Express* Power Management4.5 Direct Media Interface DMI Power Management 4.3.3 DRAM Running Average Power Limitation RAPL4.6.3 Intel Graphics Dynamic Frequency 4.6 Graphics Power Management4.6.1 Intel Rapid Memory Power Management Intel RMPM 4.6.2 Graphics Render C-StateThermal Management-Processor 5.0 Thermal ManagementProfile Desktop Processor Thermal Specifications5.1 Desktop Processor Thermal Profiles Processor-Thermal ManagementCase 5.1.1 Processor PCG 2013D Thermal ProfileTCASE = 0.33 * Power + TTV Power W5.1.2 Processor PCG 2013C Thermal Profile 5.1.3 Processor PCG 2013B Thermal Profile 5.1.4 Processor PCG 2013A Thermal Profile 37.5 37.5 5.2 Thermal Metrology5.3 Fan Speed Control Scheme with Digital Thermal Sensor DTS Measure TCASE at the geometric center of the packageΨCA = TCASE-MAX - TAMBIENT-TARGET / TDP Figure 20. Digital Thermal Sensor DTS 1.1 Definition Points5.4 Fan Speed Control Scheme with Digital Thermal Sensor DTS Thermal Margin Slope 5.5 Processor TemperatureFigure 21. Digital Thermal Sensor DTS Thermal Profile Definition Frequency Control 5.6 Adaptive Thermal MonitorCritical Temperature Flag Clock ModulationImmediate Transition to Combined TM1 and TM2 PROCHOT# Signal 5.8 Digital Thermal Sensor 5.7 THERMTRIP# Signal5.8.1 Digital Thermal Sensor Accuracy Taccuracy 5.9.1 Intel Turbo Boost Technology Power Control and Reporting5.9 Intel Turbo Boost Technology Thermal Considerations Intel Turbo Boost Technology 2.0 Package Power Control Settings 5.9.2 Package Power Control5.9.3 Turbo Time Parameter Figure 22. Package Power ControlMemory Channel A Signals 6.0 Signal Description6.1 System Memory Interface Signals Signal Description Buffer TypesSignal Description-Processor Memory Channel B SignalsSystem Memory Impedance Compensation 6.2 Memory Reference and Compensation SignalsMemory Reference and Compensation Signals DDR3/DDR3L Reference Voltage This signal is used asCFG65 PCI Express* Bifurcation 6.3 Reset and Miscellaneous SignalsReset and Miscellaneous Signals CFG3 MSR Privacy Bit FeatureDisplay Interface Signals 6.4 PCI Express*-Based Interface Signals6.5 Display Interface Signals PCI Express* Graphics Interface SignalsTestability Signals 6.7 Phase Locked Loop PLL Signals6.8 Testability Signals Phase Locked Loop PLL SignalsPower Sequencing Signals 6.9 Error and Thermal Protection Signals6.10 Power Sequencing Signals Error and Thermal Protection SignalsProcessor Power Signals 6.11 Processor Power Signals6.12 Sense Signals 6.13 Ground and Non-Critical to Function NCTF Signals7.3 VCC Voltage Identification VID 7.0 Electrical Specifications7.2 Power and Ground Lands 7.1 Integrated Voltage RegulatorElectrical Specifications-Processor Table 45. Voltage Regulator VR 12.5 Voltage Identificationcontinued Processor-Electrical Specificationscontinued continued Electrical Specifications-Processorcontinued continued Signal Groups 7.4 Reserved or Unused Signals7.5 Signal Groups DDR3 / DDR3L Compensation DDR3 / DDR3L Data SignalsDDR3 / DDR3L Reference Voltage Signals Power / Ground / OtherDigital Media Interface DMI 7.6 Test Access Port TAP Connection7.7 DC Specifications PCI Express* Graphics7.8 Voltage and Current Specifications Electrical Specifications-Processor VCCIOOUT, VCOMPOUT, and VCCIOTERM DDR3 / DDR3L Signal Group DC SpecificationsDigital Display Interface Group DC Specifications GTL Signal Group and Open Drain Signal Group DC Specifications embedded DisplayPort* eDP* Group DC SpecificationsCMOS Signal Group DC Specifications PCI Express* DC Specifications 7.8.1 Platform Environment Control Interface PECI DC CharacteristicsFigure 23. Input Device Hysteresis 7.8.2 Input Device Hysteresis8.1 Processor Component Keep-Out Zone 8.0 Package Mechanical Specifications8.2 Package Loading Specifications Figure 24. Processor Package Assembly Sketch8.3 Package Handling Guidelines 8.4 Package Insertion Specifications8.5 Processor Mass Specification Processor Loading SpecificationsFigure 25. Processor Top-Side Markings 8.7 Processor Markings8.8 Processor Land Coordinates Processor MaterialsFigure 26. Processor Package Land Coordinates 8.9 Processor Storage SpecificationsProcessor Storage Specifications TIMEsustained storage RHsustained storageProcessor Ball List by Signal Name 9.0 Processor Ball and Signal InformationProcessor Ball and Signal Information-Processor Processor-Processor Ball and Signal Information Ball # Signal NameSignal Name Signal NameBall # Signal NameSignal Name Signal NameBall # AU20 Ball # Signal NameSignal Name Signal NameBall # Signal NameSignal Name Signal NameBall # Signal NameSignal Name Signal NameBall # Signal NameSignal Name Signal Name
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BX80633I74960X, BX80646I34130, BX80646I54430, BX80646I74770K, BX80646I74770 specifications

The Intel CM8063701159502, or BX80637I53470, is a powerful CPU designed for modern computing needs. This processor belongs to Intel's 4th generation of Core i5 processors, commonly known as "Haswell". It showcases Intel's commitment to enhancing performance, increasing energy efficiency, and delivering an enriching user experience.

One of the main features of the Intel Core i5-3470 is its quad-core architecture. This allows the processor to handle multiple threads simultaneously, making it adept at multitasking and running demanding applications efficiently. With a base clock speed of 3.2 GHz, it can boost up to 3.6 GHz using Intel’s Turbo Boost technology, providing additional power when needed for intensive tasks like gaming or video editing.

The Intel i5-3470 features Intel's HD Graphics 2500, which offers decent graphics performance for everyday tasks and casual gaming. This integrated graphics solution is capable of delivering high-definition visuals and supports DirectX 11, making it suitable for lightweight gaming experiences without the need for an additional dedicated graphics card.

Another standout characteristic of the BX80637I53470 is its support for Intel Smart Cache, which is an advanced caching technology. It provides a shared cache pool that enhances performance by reducing the time it takes to access frequently used data. This feature, coupled with Intel's instruction set architecture, allows for improved processing agility and efficiency across applications.

The processor is built on a 22nm manufacturing process, which results in reduced power consumption and heat generation compared to its predecessors. It has a thermal design power (TDP) of 77 watts, making it energy efficient while still delivering robust performance. Additionally, the Core i5-3470 supports DDR3 memory, with speeds up to 1600 MHz, enabling quick data retrieval and improved system responsiveness.

Security is another important aspect of the Intel i5-3470, featuring Intel Secure Key and Intel AES New Instructions (AES-NI), which protect sensitive data and enhance encryption performance.

In conclusion, the Intel CM8063701159502, or BX80637I53470, encapsulates modern computing technology with its powerful quad-core performance, integrated graphics, energy efficiency, and robust security features, making it a versatile choice for a wide range of computing tasks. Whether users are engaging in casual gaming, productivity tasks, or multimedia consumption, this processor demonstrates a solid balance of performance and efficiency, providing an excellent computing experience overall.
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