Intel BX80646I74770S Memory Reference and Compensation Signals, Processor-Signal Description

December 2013 Order No.: 328897-004

Processor—Signal Description

Signal Name	Description	Direction / Buffer
		Type
	SDRAM Differential Clock: Channel B SDRAM Differential	O
SB_CK[3:0]	clock signal pair. The crossing of the positive edge of SB_CK
	and the negative edge of its complement SB_CK# are used to	DDR3/DDR3L
	sample the command and control signals on the SDRAM.
	Clock Enable: (1 per rank). These signals are used to:
SB_CKE[3:0]	• Initialize the SDRAMs during power-up.	O
	• Power-down SDRAM ranks.
		DDR3/DDR3L
	• Place all SDRAM ranks into and out of self-refresh during
	STR.
	Chip Select: (1 per rank). These signals are used to select	O
SB_CS#[3:0]	particular SDRAM components during the active state. There is
		DDR3/DDR3L
	one Chip Select for each SDRAM rank.
SB_ODT[3:0]	On Die Termination: Active Termination Control.	O
		DDR3/DDR3L

6.2Memory Reference and Compensation Signals

Table 32.	Memory Reference and Compensation Signals
	Signal Name	Description	Direction /
			Buffer Type
	SM_RCOMP[2:0]	System Memory Impedance Compensation:	I
			A
		DDR3/DDR3L Reference Voltage: This signal is used as	O
	SM_VREF	a reference voltage to the DDR3/DDR3L controller and is
			DDR3/DDR3L
		defined as VDDQ/2
	SA_DIMM_VREFDQ	Memory Channel A/B DIMM DQ Voltage Reference:	O
		The output pins are connected to the DIMMs, and holds
	SB_DIMM_VREFDQ		DDR3/DDR3L
		VDDQ/2 as reference voltage.

Desktop 4th Generation Intel® Core™ Processor Family, Desktop Intel® Pentium® Processor Family, and Desktop Intel® Celeron® Processor Family

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