Intel cpb4612 manual Unpacking, System Requirements, Bios Version, Connectivity

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2.1Unpacking

Check the shipping carton for damage. If the shipping carton and contents are damaged, notify the carrier and DTI for an insurance settlement. Retain the shipping carton and packing material for inspection by the carrier. Obtain authorization before returning any product to DTI. Refer to the Return Shipment Information page for assistance.

CAUTION: This board must be protected from static discharge and physical shock. Never remove any of the socketed parts except at a static-free workstation. Use the anti-static bag shipped with the product to handle the board. Wear a wrist strap grounded through one of the system's ESD Ground jacks when servicing system components.

2.2System Requirements

The following topics briefly describe the basic system requirements and configurable features of the cPB- 4612. Links are provided to other chapters and appendices containing more detailed information.

2.2.1 BIOS Version

For proper operation, the cPB-4612 must run the DTI enhanced AMI Embedded BIOS. The revision level is shown in the BIOS Identification string displayed during the Power On Self Test (POST).

2.2.2 Connectivity

The cPB-4612 features an ejector handle that is keyed for compatible slots. The board can only be inserted into slots fitted with a compatible mating key.

The cPB-4612 is designed to operate in a backplane providing CompactPCI form factor interfaces at J1, J2, J3, and J5. The J1 and J2 connectors are supplied for the CompactPCI bus, power and IPMI signals. J3 signaling must comply with the PICMG* 2.16 Packet Switching Backplane specification. The J5 interface must have through-pins for the cPB-4612 to interface with a rear panel transition card such as the cRT-4612. See the "Connectors" topic in Appendix B for connector descriptions.

2.2.3 Electrical and Environmental

The cPB-4612 meets the following requirements:

+5VDC +5%, -3% @ 6.9A typical

+3.3VDC +5%, -3% @ 2.4A typical

+12VDC ±10% @ 20mA typical

-12VDC may be required by a PMC peripheral installed on the cPB-4612.

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Image 22 Contents
CPB4612 Return Shipment Information Diversified TECHNOLOGY, INCFor Your Safety Revision History Table of Contents IntroductionConfiguration Vii Datasheet Reference CPB4612 Configuration and Maintenance GuideTables FiguresDocument Organization Chapter IntroductionProduct Definition USB PMC Features Functional BlocksCompactPCI/PSB Architecture Chipset ProcessorPCI-to-PCI Bridge Rear-Panel I/O Power Ramp CircuitryMemory and I/O Addressing Video Serial I/O 11 10/100 Ethernet Interface IDE Hard Drive InterruptsTwo-Stage Watchdog Timer Counter/TimersReset 16 DMASystem Environmental Monitor LED IndicatorsUniversal Serial Bus USB SoftwareGetting Started System Requirements Bios VersionUnpacking ConnectivityTBD Memory ConfigurationConfiguration Avg Peak 12V Avg PeakMemory Address Map Example Local DramCOM1 I/O ConfigurationPCI LPTBios Configuration Overview ConnectorsJumper Options Operating System Installation System Configuration SummaryPage Configuration PB1 Jumper Cross-Reference Table Function+5V PMC I/O 2 J16-1 BKT-GND to GND Switch Descriptions1 PB1 Reset J16-1 Function4 J16-3 +5V PMC I/O 5 J16-4 Impi Disable3 J16-2 +12V to J5-pin D1 6 J17-1 Not Used9 J17-4 Manufacture Test Mode 8 J17-3 Disable Onboard Video10 J18 Ejector Switch Reset Soft Reset Sources Reset Types and SourcesHard Reset Sources Backend Power Down SourcesNMI Sources System Monitoring and Control Monitoring and Control Functions IpmbSensors Firmware UpdatesField Replaceable Unit FRU Information SMBus Address MapIDE Controller Primary IDE Channel Features of the IDE ControllerDisk Drive Support Secondary IDE ChannelWatchdog Timer PCI Configuration Registers Watchdog Timer OverviewBase Address Register 10h WDT Configuration Register 60h WDT Lock Register 68hPreload Value 1 BAR+00h Wdtenable Watchdog EnableMemory Mapped Registers Preload Value 2 BAR+04hReload Register BAR+0Ch Bit Description Reserved Watchdog Timer Interrupt ActiveGeneral Interrupt Status BAR+08h Description Reserved PreloadValue2Enabling the Watchdog Reset Using the Watchdog in an ApplicationWatchdog Reset WDT Unlocking and Programming SequenceSystem Bios Bios Recovery Bios Upgrade and RecoveryFlash Utility Program F2 Enter Setup Space Skip Memory ESC Boot Menu Boot MenuEntering Setup… ROM Utilities ROM Utilities CPU System SummarySystem Summary Descriptions VGA RAMSystem Setup System Setup DescriptionsPage IDE Config Descriptions IDE ConfigIDE Configuration Utility Hard Disk Setup Primary Master Configuration SummaryHard Drive Setup Descriptions Boot Order Boot Order Descriptions Peripherals Onboard Peripheral Control Descriptions Console Redirection Descriptions Disabled by defaultPort Control Descriptions USB Mass Storage Config USB ConfigurationUSB Configuration Utility USB Devices DetectedUSB Mass Storage Config Descriptions USB Control DescriptionsMisc Config PCI Options DescriptionsAcpi / Power Settings PNP Options DescriptionsEvent Logging Event Logging Configuration UtilityEvent Logging Descriptions Security and ANTI-VIRUS Configuration Utility Security/VirusExit Description ExitExit Menu Plug and Play PnP PnP ISA Auto-configurationPCI Auto-configuration Resource AllocationAutomatic Detection of Video Adapters Legacy ISA ConfigurationSystem Management Bios Smbios Console RedirectionGfff Post Code LED Colors MSB-LSB Description RrrgOrrg GfrrPost Codes Trouble Shooting Hint DC Operating Characteristics SpecificationsAbsolute Maximum Ratings Reliability Battery Backup CharacteristicsOperating Temperature MechanicalBoard Dimensions and Weight Page Connectors Connector Assignments FunctionConnector Locations J5 CpldBackplane Connectors Pin Locations J15 CompactPCI Bus Connector J15 CompactPCI Bus Connector Pin outJ11 CompactPCI Bus Connector J11 CompactPCI Bus Connector Pin outJ8 CompactPCI Connector J8 Connector Pin outJ2 Rear Panel I/O CompactPCI Connector J2 Rear Panel I/O Connector Pin outJ4 Universal Serial Bus 0 Connector Pin out Pin# Function J4 Universal Serial Bus 0 connectorJ1 10/100 Ethernet J3 COM1 Serial Port J6, J7, J9, J10 64bit/66Mhz PCI Mezzanine ConnectorsPin# Function PCIAD2 GND VCC3 VIOPCIAD3 PCIAD1PAR64 Page GND Pwrviopmc 10 J12 and J13 32bit/33Mhz PCI Mezzanine ConnectorsREQ# PCIAD9 VCC Pwrviopmc GND PCIAD0VCC3 GND BUSMODE4# 11 J14 IDE Connector Page Appendix C Thermal ConsiderationsTemperature Monitoring Thermal RequirementsPage Page Datasheet Reference Appendix DIntel 855GME Chipset CompactPCIEthernet Pentium M processor Fcbga PackagePMC Specification Super I/OPage Agency Approvals Industry Canada Canada Appendix F