Intel cpb4612 10 J12 and J13 32bit/33Mhz PCI Mezzanine Connectors, REQ# PCIAD9 VCC Pwrviopmc GND

Page 90

B.10 J12 and J13 (32bit/33Mhz PCI Mezzanine Connectors)

J12 and J13 are 64-pin, 1.00mm, dual row, vertical stacking receptacles providing a PCI local bus interface to optional PMC cards. These connectors provide a complete 32-bit PCI interface. See the following "J12 PCI Mezzanine Connector Pin out" and "J13 PCI Mezzanine Connector Pin out" tables for pin definitions.

J12 – 33Mhz/32bit PMC site (JN1)

1

PMC_TCK_32_33

 

33

FRAME#

2

-12V

 

34

GND

3

GND

 

35

GND

4

INTA#

 

36

IRDY#

5

INTB#

 

37

DEVSEL#

6

INTC#

 

38

VCC

7

BUSMODE1#

 

39

GND

8

VCC

 

40

LOCK#

9

INTD#

 

41

SDONE#

10

NC

 

42

SBO#

11

GND

 

43

PAR

12

NC

 

44

GND

13

PCLKPMC

 

45

PWR_VIO_PMC

14

GND

 

46

PCI_AD(15)

15

GND

 

47

PCI_AD(12)

16

GNT#

 

48

PCI_AD(11)

17

REQ#

 

49

PCI_AD(9)

18

VCC

 

50

VCC

19

PWR_VIO_PMC

 

51

GND

20

PCI_AD(31)

 

52

CBE(0)#

21

PCI_AD(28)

 

53

PCI_AD(6)

22

PCI_AD(27)

 

54

PCI_AD(5)

23

PCI_AD(25)

 

55

PCI_AD(4)

24

GND

 

56

GND

25

GND

 

57

PWR_VIO_PMC

26

CBE(3)#

 

58

PCI_AD(3)

27

PCI_AD(22)

 

59

PCI_AD(2)

28

PCI_AD(21)

 

60

PCI_AD(1)

29

PCI_AD(19)

 

61

PCI_AD(0)

30

VCC

 

62

VCC

31

PWR_VIO_PMC

 

63

GND

32

PCI_AD(17)

 

64

REQ64#

80

Image 90 Contents
CPB4612 Return Shipment Information Diversified TECHNOLOGY, INCFor Your Safety Revision History Table of Contents IntroductionConfiguration Vii Datasheet Reference CPB4612 Configuration and Maintenance GuideTables FiguresDocument Organization Chapter IntroductionProduct Definition USB PMC Features Functional BlocksCompactPCI/PSB Architecture Processor ChipsetPCI-to-PCI Bridge Rear-Panel I/O Power Ramp CircuitryMemory and I/O Addressing VideoSerial I/O 11 10/100 Ethernet InterfaceIDE Hard Drive InterruptsTwo-Stage Watchdog Timer Counter/TimersReset 16 DMASystem Environmental Monitor LED IndicatorsUniversal Serial Bus USB SoftwareGetting Started System Requirements Bios VersionUnpacking ConnectivityTBD Memory ConfigurationConfiguration Avg Peak 12V Avg PeakMemory Address Map Example Local DramCOM1 I/O ConfigurationPCI LPTConnectors Bios Configuration OverviewJumper Options Operating System Installation System Configuration SummaryPage Configuration Jumper Cross-Reference Table Function PB1+5V PMC I/O 2 J16-1 BKT-GND to GND Switch Descriptions1 PB1 Reset J16-1 Function4 J16-3 +5V PMC I/O 5 J16-4 Impi Disable3 J16-2 +12V to J5-pin D1 6 J17-1 Not Used8 J17-3 Disable Onboard Video 9 J17-4 Manufacture Test Mode10 J18 Ejector Switch Reset Soft Reset Sources Reset Types and SourcesHard Reset Sources Backend Power Down SourcesNMI Sources System Monitoring and Control Monitoring and Control Functions IpmbSensors Firmware UpdatesField Replaceable Unit FRU Information SMBus Address MapIDE Controller Primary IDE Channel Features of the IDE ControllerDisk Drive Support Secondary IDE ChannelWatchdog Timer Watchdog Timer Overview PCI Configuration RegistersBase Address Register 10h WDT Configuration Register 60h WDT Lock Register 68hPreload Value 1 BAR+00h Wdtenable Watchdog EnableMemory Mapped Registers Preload Value 2 BAR+04hReload Register BAR+0Ch Bit Description Reserved Watchdog Timer Interrupt ActiveGeneral Interrupt Status BAR+08h Description Reserved PreloadValue2Enabling the Watchdog Reset Using the Watchdog in an ApplicationWatchdog Reset WDT Unlocking and Programming SequenceSystem Bios Bios Upgrade and Recovery Bios RecoveryFlash Utility Program Boot Menu F2 Enter Setup Space Skip Memory ESC Boot MenuEntering Setup… ROM Utilities ROM Utilities CPU System SummarySystem Summary Descriptions VGA RAMSystem Setup System Setup DescriptionsPage IDE Config IDE Config DescriptionsIDE Configuration Utility Hard Disk Setup Primary Master Configuration SummaryHard Drive Setup Descriptions Boot Order Boot Order Descriptions Peripherals Console Redirection Descriptions Disabled by default Onboard Peripheral Control DescriptionsPort Control Descriptions USB Mass Storage Config USB ConfigurationUSB Configuration Utility USB Devices DetectedUSB Mass Storage Config Descriptions USB Control DescriptionsMisc Config PCI Options DescriptionsAcpi / Power Settings PNP Options DescriptionsEvent Logging Configuration Utility Event LoggingEvent Logging Descriptions Security and ANTI-VIRUS Configuration Utility Security/VirusExit Exit DescriptionExit Menu Plug and Play PnP PnP ISA Auto-configurationPCI Auto-configuration Resource AllocationAutomatic Detection of Video Adapters Legacy ISA ConfigurationSystem Management Bios Smbios Console RedirectionGfff Post Code LED Colors MSB-LSB Description RrrgOrrg GfrrPost Codes Trouble Shooting Hint Specifications DC Operating CharacteristicsAbsolute Maximum Ratings Reliability Battery Backup CharacteristicsOperating Temperature MechanicalBoard Dimensions and Weight Page Connectors Connector Assignments FunctionConnector Locations J5 CpldBackplane Connectors Pin Locations J15 CompactPCI Bus Connector J15 CompactPCI Bus Connector Pin outJ11 CompactPCI Bus Connector J11 CompactPCI Bus Connector Pin outJ8 CompactPCI Connector J8 Connector Pin outJ2 Rear Panel I/O CompactPCI Connector J2 Rear Panel I/O Connector Pin outJ4 Universal Serial Bus 0 connector J4 Universal Serial Bus 0 Connector Pin out Pin# FunctionJ1 10/100 Ethernet J6, J7, J9, J10 64bit/66Mhz PCI Mezzanine Connectors J3 COM1 Serial Port Pin# Function PCIAD2 GND VCC3 VIOPCIAD3 PCIAD1PAR64 Page GND Pwrviopmc 10 J12 and J13 32bit/33Mhz PCI Mezzanine ConnectorsREQ# PCIAD9 VCC Pwrviopmc GND PCIAD0VCC3 GND BUSMODE4# 11 J14 IDE Connector Page Appendix C Thermal ConsiderationsTemperature Monitoring Thermal RequirementsPage Page Datasheet Reference Appendix DIntel 855GME Chipset CompactPCIEthernet Pentium M processor Fcbga PackagePMC Specification Super I/OPage Agency Approvals Industry Canada Canada Appendix F