Intel cpb4612 manual 11 10/100 Ethernet Interface, IDE Hard Drive, Serial I/O, Interrupts

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Access Controller (MAC) and the physical layer (PHY) interface combined into a single component solution. Both Ethernet Channels are directed to the rear connector at J3 for PICMG 2.16 support.

The "Ethernet" topic in Appendix D contains links to the datasheets for the Ethernet devices used on the cPB-4612.

1.3.11 10/100 Ethernet Interface

The cPB-4612 supports one 10/100 Base-TX Ethernet interface. The Intel 82559EM Ethernet controller provides this interface. The NIC address programmed into the controller is located on labels on the board. Link and activity LED signals are on the front panel at the RJ-45 connector.

The "Ethernet" topic in Appendix D contains links to the datasheets for the Ethernet devices used on the cPB-4612.

1.3.12 IDE Hard Drive

The cPB-4612 w/IDE supports an onboard ATA/100 2.5” IDE interface. This can be used to connect a 2.5” hard drive. The IDE interface is implemented using Intel’s 6300ESB I/O Controller Hub (ICH). Note that the onboard 2.5” IDE connector is not present on versions of the board that support the 33MHz/32 bit PMC site.

All versions of the cPB-4612 supports a second ATA/100 IDE interface through the CompactPCI J5 connector. The IDE interface is implemented using Intel’s 6300ESB I/O Controller Hub (ICH).

All versions of the cPB-4612 supports a Serial ATA/150 interface through the CompactPCI J5 connector. The IDE interface is implemented using Intel’s 6300ESB I/O Controller Hub (ICH).

Both the 2.5” IDE drive connector and 33Mhz/32bit PMC site cannot both be present at the same time, since they are in the same physical space on the board. Which one is populated depends on the version of the board.

See Chapter 6, "IDE Controller", for more information.

1.3.13 Serial I/O

The cPB-4612 provides support for two RS-232 compatible serial ports. COM1 is accessible at the faceplate through a 9-pin DSUB connector. This port is typically used for test access. COM2 is available at the J5 Rear Panel I/O connector.

The serial port interface is implemented using Intel’s 6300ESB I/O Controller Hub (ICH).

1.3.14 Interrupts

Two enhanced, 8259-style interrupt controllers provide the cPB-4612 with a total of 15 interrupt inputs. Interrupt controller features include support for:

Level-triggered and edge-triggered inputs

Individual input masking

Fixed and rotating priorities

Interrupt sources include:

Counter/Timers

Serial I/O

Keyboard

Floppy disk

IDE interface

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CPB4612 Return Shipment Information Diversified TECHNOLOGY, INCFor Your Safety Revision History Table of Contents IntroductionConfiguration Vii Datasheet Reference CPB4612 Configuration and Maintenance GuideTables FiguresDocument Organization Chapter IntroductionProduct Definition USB PMC Features Functional BlocksCompactPCI/PSB Architecture Processor ChipsetPCI-to-PCI Bridge Rear-Panel I/O Power Ramp CircuitryMemory and I/O Addressing VideoSerial I/O 11 10/100 Ethernet InterfaceIDE Hard Drive InterruptsTwo-Stage Watchdog Timer Counter/TimersReset 16 DMASystem Environmental Monitor LED IndicatorsUniversal Serial Bus USB SoftwareGetting Started System Requirements Bios VersionUnpacking ConnectivityTBD Memory ConfigurationConfiguration Avg Peak 12V Avg PeakMemory Address Map Example Local DramCOM1 I/O ConfigurationPCI LPTConnectors Bios Configuration OverviewJumper Options Operating System Installation System Configuration SummaryPage Configuration Jumper Cross-Reference Table Function PB1+5V PMC I/O 2 J16-1 BKT-GND to GND Switch Descriptions1 PB1 Reset J16-1 Function4 J16-3 +5V PMC I/O 5 J16-4 Impi Disable3 J16-2 +12V to J5-pin D1 6 J17-1 Not Used8 J17-3 Disable Onboard Video 9 J17-4 Manufacture Test Mode10 J18 Ejector Switch Reset Soft Reset Sources Reset Types and SourcesHard Reset Sources Backend Power Down SourcesNMI Sources System Monitoring and Control Monitoring and Control Functions IpmbSensors Firmware UpdatesField Replaceable Unit FRU Information SMBus Address MapIDE Controller Primary IDE Channel Features of the IDE ControllerDisk Drive Support Secondary IDE ChannelWatchdog Timer Watchdog Timer Overview PCI Configuration RegistersBase Address Register 10h WDT Configuration Register 60h WDT Lock Register 68hPreload Value 1 BAR+00h Wdtenable Watchdog EnableMemory Mapped Registers Preload Value 2 BAR+04hReload Register BAR+0Ch Bit Description Reserved Watchdog Timer Interrupt ActiveGeneral Interrupt Status BAR+08h Description Reserved PreloadValue2Enabling the Watchdog Reset Using the Watchdog in an ApplicationWatchdog Reset WDT Unlocking and Programming SequenceSystem Bios Bios Upgrade and Recovery Bios RecoveryFlash Utility Program Boot Menu F2 Enter Setup Space Skip Memory ESC Boot MenuEntering Setup… ROM Utilities ROM Utilities CPU System SummarySystem Summary Descriptions VGA RAMSystem Setup System Setup DescriptionsPage IDE Config IDE Config DescriptionsIDE Configuration Utility Hard Disk Setup Primary Master Configuration SummaryHard Drive Setup Descriptions Boot Order Boot Order Descriptions Peripherals Console Redirection Descriptions Disabled by default Onboard Peripheral Control DescriptionsPort Control Descriptions USB Mass Storage Config USB ConfigurationUSB Configuration Utility USB Devices DetectedUSB Mass Storage Config Descriptions USB Control DescriptionsMisc Config PCI Options DescriptionsAcpi / Power Settings PNP Options DescriptionsEvent Logging Configuration Utility Event LoggingEvent Logging Descriptions Security and ANTI-VIRUS Configuration Utility Security/VirusExit Exit DescriptionExit Menu Plug and Play PnP PnP ISA Auto-configurationPCI Auto-configuration Resource AllocationAutomatic Detection of Video Adapters Legacy ISA ConfigurationSystem Management Bios Smbios Console RedirectionGfff Post Code LED Colors MSB-LSB Description RrrgOrrg GfrrPost Codes Trouble Shooting Hint Specifications DC Operating CharacteristicsAbsolute Maximum Ratings Reliability Battery Backup CharacteristicsOperating Temperature MechanicalBoard Dimensions and Weight Page Connectors Connector Assignments FunctionConnector Locations J5 CpldBackplane Connectors Pin Locations J15 CompactPCI Bus Connector J15 CompactPCI Bus Connector Pin outJ11 CompactPCI Bus Connector J11 CompactPCI Bus Connector Pin outJ8 CompactPCI Connector J8 Connector Pin outJ2 Rear Panel I/O CompactPCI Connector J2 Rear Panel I/O Connector Pin outJ4 Universal Serial Bus 0 connector J4 Universal Serial Bus 0 Connector Pin out Pin# FunctionJ1 10/100 Ethernet J6, J7, J9, J10 64bit/66Mhz PCI Mezzanine Connectors J3 COM1 Serial PortPin# Function PCIAD2 GND VCC3 VIOPCIAD3 PCIAD1PAR64 Page GND Pwrviopmc 10 J12 and J13 32bit/33Mhz PCI Mezzanine ConnectorsREQ# PCIAD9 VCC Pwrviopmc GND PCIAD0VCC3 GND BUSMODE4# 11 J14 IDE Connector Page Appendix C Thermal ConsiderationsTemperature Monitoring Thermal RequirementsPage Page Datasheet Reference Appendix DIntel 855GME Chipset CompactPCIEthernet Pentium M processor Fcbga PackagePMC Specification Super I/OPage Agency Approvals Industry Canada Canada Appendix F