Intel cpci borard with a intel pentuim M Using the Watchdog in an Application, Watchdog Reset

Page 47

7.4Using the Watchdog in an Application

The following topics are provided to aid you in learning to use watchdog in an application.

7.4.1 WDT Unlocking and Programming Sequence

Unlocking and programming the WDT Memory Mapped registers involves the following sequence:

1.Write “80” to the Reload Register (offset BAR + 0Ch)

2.Write “86” to the Reload Register (offset BAR + 0Ch)

3.Write to desired memory mapped register (offset BAR + 0Xh)

7.4.2Watchdog Reset

An application using the reset feature sets the preload values, enables the watchdog reset, and then periodically reloads the watchdog to keep it from resetting the system. If a reload is missed, the watchdog times out and resets the system hardware.

7.4.2.1Load Preload Values

The following is an algorithm for loading the preload values :

1.If the value desired falls between 1ms and 10min, clear bit 2 WDT_PRE_SEL of the WDT Configuration Register. Else if the value desired falls between 1µs and 1sec set bit 2 of the WDT Configuration Register.

2.Write “80” to the memory mapped Reload Register (offset BAR + 0Ch)

3.Write “86” to the memory mapped Reload Register (offset BAR + 0Ch)

4.Write desired value to the memory mapped Preload Value 1 register (offset BAR + 00h)

5.Write “80” to the memory mapped Reload Register (offset BAR + 0Ch)

6.Write “86” to the memory mapped Reload Register (offset BAR + 0Ch)

7.Write desired value to the memory mapped Preload Value 2 register (offset BAR + 04h)

7.4.2.2Enabling the Watchdog Reset

To enable the watchdog do the following

1. Set bit 1 of the WDT Lock Register to ‘1’ to enable the watchdog timer.

7.4.2.3Reloading the Watchdog

Once the watchdog is enabled, it must be periodically reloaded within the terminal count period to avoid resetting the system hardware. This should be done by the following:

1.Write “80” to the memory mapped Reload Register (offset BAR + 0Ch)

2.Write “86” to the memory mapped Reload Register (offset BAR + 0Ch)

3.Write ‘1’ to bit 8 WDT_RELOAD in the Reload Register (offset BAR + 0Ch)

37

Image 47 Contents
CPB4612 Diversified TECHNOLOGY, INC Return Shipment InformationFor Your Safety Revision History Introduction Table of ContentsConfiguration Vii CPB4612 Configuration and Maintenance Guide Datasheet ReferenceFigures TablesDocument Organization Introduction ChapterProduct Definition USB PMC Functional Blocks FeaturesCompactPCI/PSB Architecture PCI-to-PCI Bridge ProcessorChipset Video Power Ramp CircuitryMemory and I/O Addressing Rear-Panel I/OInterrupts 11 10/100 Ethernet InterfaceIDE Hard Drive Serial I/O16 DMA Counter/TimersReset Two-Stage Watchdog TimerSoftware LED IndicatorsUniversal Serial Bus USB System Environmental MonitorGetting Started Connectivity Bios VersionUnpacking System Requirements12V Avg Peak Memory ConfigurationConfiguration Avg Peak TBDLocal Dram Memory Address Map ExampleLPT I/O ConfigurationPCI COM1Jumper Options ConnectorsBios Configuration Overview System Configuration Summary Operating System InstallationPage Configuration +5V PMC I/O Jumper Cross-Reference Table FunctionPB1 J16-1 Function Switch Descriptions1 PB1 Reset 2 J16-1 BKT-GND to GND6 J17-1 Not Used 5 J16-4 Impi Disable3 J16-2 +12V to J5-pin D1 4 J16-3 +5V PMC I/O10 J18 Ejector Switch 8 J17-3 Disable Onboard Video9 J17-4 Manufacture Test Mode Reset Backend Power Down Sources Reset Types and SourcesHard Reset Sources Soft Reset SourcesNMI Sources System Monitoring and Control Ipmb Monitoring and Control FunctionsSMBus Address Map Firmware UpdatesField Replaceable Unit FRU Information SensorsIDE Controller Secondary IDE Channel Features of the IDE ControllerDisk Drive Support Primary IDE ChannelWatchdog Timer Base Address Register 10h Watchdog Timer Overview PCI Configuration Registers WDT Lock Register 68h WDT Configuration Register 60hPreload Value 2 BAR+04h Wdtenable Watchdog EnableMemory Mapped Registers Preload Value 1 BAR+00hDescription Reserved PreloadValue2 Bit Description Reserved Watchdog Timer Interrupt ActiveGeneral Interrupt Status BAR+08h Reload Register BAR+0ChWDT Unlocking and Programming Sequence Using the Watchdog in an ApplicationWatchdog Reset Enabling the Watchdog ResetSystem Bios Flash Utility Program Bios Upgrade and RecoveryBios Recovery Entering Setup… Boot MenuF2 Enter Setup Space Skip Memory ESC Boot Menu ROM Utilities ROM Utilities VGA RAM System SummarySystem Summary Descriptions CPUSystem Setup Descriptions System SetupPage IDE Configuration Utility IDE ConfigIDE Config Descriptions Primary Master Configuration Summary Hard Disk SetupHard Drive Setup Descriptions Boot Order Boot Order Descriptions Peripherals Port Control Descriptions Console Redirection Descriptions Disabled by defaultOnboard Peripheral Control Descriptions USB Devices Detected USB ConfigurationUSB Configuration Utility USB Mass Storage ConfigUSB Control Descriptions USB Mass Storage Config DescriptionsPCI Options Descriptions Misc ConfigPNP Options Descriptions Acpi / Power SettingsEvent Logging Descriptions Event Logging Configuration UtilityEvent Logging Security/Virus Security and ANTI-VIRUS Configuration UtilityExit Menu ExitExit Description Resource Allocation PnP ISA Auto-configurationPCI Auto-configuration Plug and Play PnPConsole Redirection Legacy ISA ConfigurationSystem Management Bios Smbios Automatic Detection of Video AdaptersGfrr Post Code LED Colors MSB-LSB Description RrrgOrrg GfffPost Codes Trouble Shooting Hint Absolute Maximum Ratings SpecificationsDC Operating Characteristics Mechanical Battery Backup CharacteristicsOperating Temperature ReliabilityBoard Dimensions and Weight Page Connector Assignments Function ConnectorsJ5 Cpld Connector LocationsBackplane Connectors Pin Locations J15 CompactPCI Bus Connector Pin out J15 CompactPCI Bus ConnectorJ11 CompactPCI Bus Connector Pin out J11 CompactPCI Bus ConnectorJ8 Connector Pin out J8 CompactPCI ConnectorJ2 Rear Panel I/O Connector Pin out J2 Rear Panel I/O CompactPCI ConnectorJ1 10/100 Ethernet J4 Universal Serial Bus 0 connectorJ4 Universal Serial Bus 0 Connector Pin out Pin# Function Pin# Function J6, J7, J9, J10 64bit/66Mhz PCI Mezzanine ConnectorsJ3 COM1 Serial Port PCIAD1 GND VCC3 VIOPCIAD3 PCIAD2PAR64 Page PCIAD0 10 J12 and J13 32bit/33Mhz PCI Mezzanine ConnectorsREQ# PCIAD9 VCC Pwrviopmc GND GND PwrviopmcVCC3 GND BUSMODE4# 11 J14 IDE Connector Page Thermal Considerations Appendix CThermal Requirements Temperature MonitoringPage Page Appendix D Datasheet ReferencePentium M processor Fcbga Package CompactPCIEthernet Intel 855GME ChipsetSuper I/O PMC SpecificationPage Agency Approvals Industry Canada Canada Appendix F