7.1Watchdog Timer Overview
The watchdog timer is implemented by using the 6300ESB ICH integrated watchdog timer. The primary function of the watchdog timer is to monitor the
•
•Enabled and disabled through software control
•Armed and strobed through software control
The watchdog timer drives the First and Second Stages as follows:
1.The watchdog times out (First Stage) after a selected timeout interval.
2.SMI or IRQ is driven high.
3.A hard reset occurs (Second Stage) after a selected timeout interval.
The watchdog timer can have a range from 1µs to 10 minutes. The timer uses a 35 bit down counter. The counter is loaded with the first preload register. The timer is then enabled and it starts counting down. This is called the first stage. If the counter reaches zero before being reloaded, the watchdog timer generates an internal interrupt. The counter is then loaded with the second preload register and starts counting down. This is called the second stage. If the counter reaches zero before being reloaded, the watchdog timer drives the WDT_TOUT pin low until the system is reset.
More information can be obtained from the Intel 6300ESB Datasheet. The "Intel 855GME Chipset" topic in Appendix D provides a link to the 6300ESB datasheet.
7.2PCI Configuration Registers
The two stage watchdog timer controller appears in PCI config space at Bus:0 Dev:29 Func:4. The following registers are the primary PCI registers to control the watchdog timer.
7.2.1 Base Address Register (10h)
Offset: | 10h |
Default Value: | 00000000h |
Size: | 32 bits |
Attribute: | R/W |
Bit
31:4
3
2:1
0
Description
Base Address
Base address points to the memory mapped region
Prefetchable
Type
Resource Type Indicator
33