IBM EM78P312N manual Time Base Timer and Keytone Generator, Address Name Bit

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EM78P312N

8-Bit Microcontroller

5.6 Time Base Timer and Keytone Generator

Registers for AD Converter Circuit

R_BANK

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 1

0X0E

TBKTC

TEN

TCK1

TCK0

0

TBTEN

TBTCK2

TBTCK1

TBTCK0

R/W

R/W

R/W

--

R/W

R/W

R/W

R/W

Bank 0

0x0F

ISFR2

0

UERRIF

RBFF

TBEF

TBIF

EXIF1

0

TCIF0

0

R/W

R/W

R/W

R/W

R/W

0

R/W

SPR

0x0F

IMR2

0

UERRIE

URIE

UTIE

TBIE

EXIE1

0

TCIE0

0

R/W

R/W

R/W

R/W

R/W

0

R/W

Output Latch

Output Enable (P63)

Data Output

D

Q

Fosc/213

/TONE Pin

Fosc/212

MUX

11

Fosc/2

Fosc/210

TEN

TCK1:0

2

TBKTC

Fig. 5-6 Tone Output Pin Configuration

The Keytone output can generate 50% duty pulse for driving a piezo-electric buzzer. The P63 must be set to “1” before the keytone is enabled and it can be halted by setting P63 to “0”.

P63

TEN

TONE Pin

Fig. 5-7 Tone Output Pin Timing Chart

26 •	Product Specification (V1.0) 10.03.2006

(This specification is subject to change without further notice)

Image 30

Contents EM78P312N DOC. VersionElan Microelectronics Corporation Contents 16.2 14.116.1 16.3General Description Bit MicrocontrollerSymbol Pin No Type Function Pin DescriptionFunctional Block Diagram Function DescriptionOperating Registers Operating RegistersBit Microcontroller R0 Indirect Addressing Register R1 Time Clock /CounterR2 Program Counter & Stack Bit 7 ~ Bit 6 RBS1 ~ RBS0 R-Register page select User Memory SpaceR3 Status Register RBS1 RBS0Bit 0 C Carry flag R4 RAM Select Register Bit 1 SIS Sleep and Idle mode selectSIS = 0 Idle mode SIS = 1 Sleep mode R5 System Control RegisterBit 7 ~ Bit 0 P67 ~ P60 8-bit Port 6 I/O data register RB Timer/Counter 4 Control RegisterBit Microcontroller R6 Port 6 I/O Data Register R7 Port 7 I/O Data RegisterTC4CK2 TC4CK1 TC4CK0 RC Timer 4 Data BufferClock Source Resolution Max. Time Fosc=8MBit Microcontroller RE Interrupt Status Flag Register RFInterrupt Status Flag RegisterBank 1 R7 TC3DB Timer 3 Data Buffer B Bank 1 R5 TC3CR Timer/Counter 3 Control RegisterTC3M = 1 Capture mode Bank 1 R6 TC3DA Timer 3 Data Buffer a Bit 7 TC3CAP Software capture controlTC2S = 0 Stop and counter clear Bank 1 R9 TC2DH Timer 2 Data Buffer High ByteBank 1 RA TC2DL Timer 2 Data Buffer Low Byte Bank 1 RB Adcr AD Control RegisterBank 1 RC Adic AD Input Pin Control Bit 7 ~ Bit 0 ADE7 ~ ADE0 AD input pin enable controlBit 5~ Bit 4 ADCK1 ~ ADCK0 AD Conversion Time Select Bank 1 RD Addh AD High 8-bit Data BufferBank 2 R5 URC1 Uart Control Register TEN = 0 Disable TEN = 1 EnableBit Microcontroller Bank 1 RE Tbktc TBT/Keytone Control BitBRATE2 BRATE1 BRATE0 Bank 2 R7 URS Uart Status RegisterBit 7 URRD8 Receiving data Bit TC2CK1 TC2CK0Even = 0 Odd parity Even = 1 Even parity Bit 5 PRE Enable parity additionBit 6 Even Select parity check Bank 2 R9 Urtd Uart Transmit Data BufferEDS = 0 Rising edge EDS = 1 Falling edge Bit 5 ~ Bit 3 BRS0 ~ BRS2 SPI Clock Source SelectBit 2 EDS Data shift out edge select Bit 0 WBE Write buffer empty flag. Read onlyBank 3 RB PLC1 Pull Low Control Register PHE6x = 1 Disable P6x pull highTransfer Mode SPID7 SPID6 SPID5 SPID4 SPID3 SPID2 SPID1 SPID0Special Purpose Registers INT1ES = 0 Rising edge INT1ES = 1 Falling edge IOC6 ~ IOC9 − I/O Port Control RegisterIntcr − INT Control Register Address 0Bh TC2ES = 0 Rising edge TC2ES = 1 Falling edgeExternal Interrupt Adoscr − AD Offset Control Register Address 0ChCali Sign IMR2 − Interrupt Mask Register 2 Address 0Fh Uerrie Urie Utie Tbie EXIE1 TCIE0Mode Switching Control CPU Operation ModeRegisters for CPU Operation Mode Operation ModeAD Converter Sleep Mode Idle ModeWake-up Signal R5 SIS = 1+SLEP R5 SIS= 0 + Slep Instruction Wake-up MethodsSampling Time Operation Mode Max. Frequency Max. Conversion Rate per BitADC Data Register Conversion TimeTime Base Timer and Keytone Generator Address Name BitMUX Uart Universal Asynchronous Receiver/Transmitter Registers for Uart CircuitName Bit Uart Mode TransmittingReceiving Baud Rate GeneratorSPI Serial Peripheral Interface Registers for the SPI CircuitRbank Address Name Bit Bit Transmit Mode Shift Direction and Sample PhaseTransfer Mode Serial ClockBit Microcontroller Bit Receive Mode Bit Transmit/Receive ModeSCK pin Spis Multiple Device Connect /SSTimer/Counter Registers for Timer/Counter 2 CircuitTimer Mode Counter ModeWindow Mode Registers for Timer/Counter 3 Circuit 21 Window Mode Timing ChartCapture Mode 22 Configuration of Timer/Counter3Registers for Timer 4 Circuit TCIF4PDO Mode TCR4Up-counter PWM Mode12 TCC/WDT & Prescaler TC4 InterruptReset and Wake-up Reset13 I/O Ports Wake-up from Sleep Mode Wake-up from Idle ModeAddress Name Reset Type Bit Summary of the Initialized Values for RegistersBit Microcontroller Register Bank SCRAddres URTD8 Bit Microcontroller General Purpose Registers Reset TypeStatus of RST, T, and P of the Status Register Events that may affect the T and P Status28 Controller Reset Block Diagram InterruptCrystal Oscillator/Ceramic Resonators Crystal OscillatorOscillator Modes Summary of Maximum Operating SpeedsOscillator Type Frequency Mode Frequency C1 pF C2 pF 740 EM78P312N 809NExternal RC Oscillator Mode OS CICode Option Register Word Enwdtb = 0 Enable Enwdtb = 1 DisableCode Option Register Bit 12 ~ 9 Not usedCustomer ID Register Power-on ConsiderationsExternal Power-on Reset Circuit OSC = 0 RC type OSC = 1 Crystal typeEM78P312N Residue-Voltage ProtectionVdd EM78P809NInstruction Set Binary Instruction Hex Mnemonic Operation StatusBinary Instruction Hex Mnemonic Operation Status Affected DECRecommended Operating Conditions Symbol Parameter Condition Min Typ Max UnitAbsolute Maximum Ratings Vss =DC Electrical Characteristics Ta= 25 C, VDD= 5.0V ± 5%, VSS=Ta= 25 C, VDD= 3.0V ± 5%, VSS= Varef AC Electrical Characteristic Symbol Parameter Conditions Min Typ Max UnitTa=- 40C ~ 85 C, VDD=5V ± 5%, VSS=0V Timing Diagram AC Test Input/Output WaveformPin Count Package Size OTP MCUPackage Type EM78P311SxY