IBM EM78P312N manual 12 TCC/WDT & Prescaler, PWM Mode, Up-counter, TC4 Interrupt

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EM78P312N

8-Bit Microcontroller

5.11.4 PWM Mode

In Pulse Width Modulation (PWM) Output mode, counting up is performed using the internal clock. The contents of the TCR4 are compared with the contents of the up-counter. The F/F is toggled when match is found. The counter is still counting, the F/F is toggled again when the counter overflows, then the counter is cleared. The F/F output is inverted and output to the /PWM pin. A TC4 interrupt is generated each time an overflow occurs. TCR4 is configured as a 2-stage shift register and, during output, will not switch until one output cycle is completed even if TCR4 is overwritten. Therefore, the output can be changed continuously. TRC4 is also shifted the first time by setting TC4S to “1” after data is loaded to TCR4.

Source Clock

Up-counter

0

1

n-1

n

n+1 n+2

FE

FF 0

n-1

n

n+1 n+2

FE

FF

0

1

m-1

m

TCR4

n/n

Overflow

n/m

m/m

Match

Match

Overflow

Shift

F/F

Overwrite

/PWM

TC4 Interrupt

1 Period

Fig. 5-26 Timing Chart for PWM Mode

5.12 TCC/WDT & Prescaler

An 8-bit counter is available as prescaler for the TCC. The PSR0~PSR2 bits determine the ratio. The prescaler is cleared each time the instruction is written to TCC under TCC mode.

R1 (TCC) is an 8-bit timer/counter. The clock source of TCC is the internal clock. If the TCC signal source is from the internal clock, TCC will increase by 1 at every instruction cycle (without prescaler). CLK=Fosc/2 or CLK=Fosc/4 selection is determined by the CODE Option bit CLK status. CLK=Fosc/2 is used if CLK bit is "0", and CLK=Fosc/4 is used if CLK bit is "1".

The watchdog timer is a free running on-chip RC oscillator. During normal operation mode, a WDT time-out (if enabled) will cause the device to reset or interrupt by setting WDTO. The WDT can be enabled or disabled any time during normal mode by software programming. Without prescaler, the WDT time-out period is approximately 18 ms (default). The WDT can also be used as a timer to generate an interrupt at fixed interval.

Product Specification (V1.0) 10.03.2006

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(This specification is subject to change without further notice)

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Contents DOC. Version EM78P312NElan Microelectronics Corporation Contents 16.1 14.116.2 16.3Bit Microcontroller General DescriptionPin Description Symbol Pin No Type FunctionFunction Description Functional Block DiagramOperating Registers Operating RegistersBit Microcontroller R0 Indirect Addressing Register R1 Time Clock /CounterR2 Program Counter & Stack R3 Status Register User Memory SpaceBit 7 ~ Bit 6 RBS1 ~ RBS0 R-Register page select RBS1 RBS0SIS = 0 Idle mode SIS = 1 Sleep mode Bit 1 SIS Sleep and Idle mode selectBit 0 C Carry flag R4 RAM Select Register R5 System Control RegisterBit Microcontroller R6 Port 6 I/O Data Register RB Timer/Counter 4 Control RegisterBit 7 ~ Bit 0 P67 ~ P60 8-bit Port 6 I/O data register R7 Port 7 I/O Data RegisterClock Source Resolution Max. Time RC Timer 4 Data BufferTC4CK2 TC4CK1 TC4CK0 Fosc=8MRFInterrupt Status Flag Register Bit Microcontroller RE Interrupt Status Flag RegisterTC3M = 1 Capture mode Bank 1 R6 TC3DA Timer 3 Data Buffer a Bank 1 R5 TC3CR Timer/Counter 3 Control RegisterBank 1 R7 TC3DB Timer 3 Data Buffer B Bit 7 TC3CAP Software capture controlBank 1 RA TC2DL Timer 2 Data Buffer Low Byte Bank 1 R9 TC2DH Timer 2 Data Buffer High ByteTC2S = 0 Stop and counter clear Bank 1 RB Adcr AD Control RegisterBit 5~ Bit 4 ADCK1 ~ ADCK0 AD Conversion Time Select Bit 7 ~ Bit 0 ADE7 ~ ADE0 AD input pin enable controlBank 1 RC Adic AD Input Pin Control Bank 1 RD Addh AD High 8-bit Data BufferBit Microcontroller Bank 1 RE Tbktc TBT/Keytone Control TEN = 0 Disable TEN = 1 EnableBank 2 R5 URC1 Uart Control Register BitBit 7 URRD8 Receiving data Bit Bank 2 R7 URS Uart Status RegisterBRATE2 BRATE1 BRATE0 TC2CK1 TC2CK0Bit 6 Even Select parity check Bit 5 PRE Enable parity additionEven = 0 Odd parity Even = 1 Even parity Bank 2 R9 Urtd Uart Transmit Data BufferBit 2 EDS Data shift out edge select Bit 5 ~ Bit 3 BRS0 ~ BRS2 SPI Clock Source SelectEDS = 0 Rising edge EDS = 1 Falling edge Bit 0 WBE Write buffer empty flag. Read onlyTransfer Mode PHE6x = 1 Disable P6x pull highBank 3 RB PLC1 Pull Low Control Register SPID7 SPID6 SPID5 SPID4 SPID3 SPID2 SPID1 SPID0Special Purpose Registers Intcr − INT Control Register Address 0Bh IOC6 ~ IOC9 − I/O Port Control RegisterINT1ES = 0 Rising edge INT1ES = 1 Falling edge TC2ES = 0 Rising edge TC2ES = 1 Falling edgeExternal Interrupt Adoscr − AD Offset Control Register Address 0ChCali Sign Uerrie Urie Utie Tbie EXIE1 TCIE0 IMR2 − Interrupt Mask Register 2 Address 0FhRegisters for CPU Operation Mode CPU Operation ModeMode Switching Control Operation ModeWake-up Signal R5 SIS = 1+SLEP R5 SIS= 0 + Slep Instruction Sleep Mode Idle ModeAD Converter Wake-up MethodsADC Data Register Operation Mode Max. Frequency Max. Conversion Rate per BitSampling Time Conversion TimeAddress Name Bit Time Base Timer and Keytone GeneratorMUX Uart Universal Asynchronous Receiver/Transmitter Registers for Uart CircuitName Bit Transmitting Uart ModeBaud Rate Generator ReceivingSPI Serial Peripheral Interface Registers for the SPI CircuitRbank Address Name Bit Transfer Mode Shift Direction and Sample PhaseBit Transmit Mode Serial ClockBit Microcontroller Bit Receive Mode Bit Transmit/Receive ModeSCK pin Multiple Device Connect /SS SpisRegisters for Timer/Counter 2 Circuit Timer/CounterTimer Mode Counter ModeWindow Mode 21 Window Mode Timing Chart Registers for Timer/Counter 3 Circuit22 Configuration of Timer/Counter3 Capture ModeTCIF4 Registers for Timer 4 CircuitTCR4 PDO Mode12 TCC/WDT & Prescaler PWM ModeUp-counter TC4 InterruptReset and Wake-up Reset13 I/O Ports Wake-up from Idle Mode Wake-up from Sleep ModeSummary of the Initialized Values for Registers Address Name Reset Type BitSCR Bit Microcontroller Register BankAddres URTD8 Status of RST, T, and P of the Status Register Reset TypeBit Microcontroller General Purpose Registers Events that may affect the T and P StatusInterrupt 28 Controller Reset Block DiagramOscillator Modes OscillatorCrystal Oscillator/Ceramic Resonators Crystal Summary of Maximum Operating Speeds740 EM78P312N 809N Oscillator Type Frequency Mode Frequency C1 pF C2 pFOS CI External RC Oscillator ModeCode Option Register Enwdtb = 0 Enable Enwdtb = 1 DisableCode Option Register Word Bit 12 ~ 9 Not usedExternal Power-on Reset Circuit Power-on ConsiderationsCustomer ID Register OSC = 0 RC type OSC = 1 Crystal typeVdd Residue-Voltage ProtectionEM78P312N EM78P809NBinary Instruction Hex Mnemonic Operation Status Instruction SetDEC Binary Instruction Hex Mnemonic Operation Status AffectedAbsolute Maximum Ratings Symbol Parameter Condition Min Typ Max UnitRecommended Operating Conditions Vss =Ta= 25 C, VDD= 5.0V ± 5%, VSS= DC Electrical CharacteristicsTa= 25 C, VDD= 3.0V ± 5%, VSS= Varef AC Electrical Characteristic Symbol Parameter Conditions Min Typ Max UnitTa=- 40C ~ 85 C, VDD=5V ± 5%, VSS=0V AC Test Input/Output Waveform Timing DiagramPackage Type OTP MCUPin Count Package Size EM78P311SxY