IBM EM78P312N manual SPI Serial Peripheral Interface, Registers for the SPI Circuit

Page 35

EM78P312N

8-Bit Microcontroller

5.8 SPI (Serial Peripheral Interface)

Registers for the SPI Circuit

R_BANK Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

	Bank 3	0X05	SPIC1	SMP	DCOL	BRS2	BRS1	BRS0	EDS	DORD	WBE
	Bank 3	0X05	SPIC1	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R
				R/W	R/W	R/W	R/W	R/W	R/W	R/W	R

	Bank 3	0X06	SPIC2	SPIS	0	0	0	0	SPIM1	SPIM0	RBF
	Bank 3	0X06	SPIC2	R/W	--	--	--	--	R/W	R/W	R
				R/W	--	--	--	--	R/W	R/W	R

	Bank 3	0X07	SPID	SPID7	SPID6	SPID5	SPID4	SPID3	SPID2	SPID1	SPID0
	Bank 3	0X07	SPID	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
				R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W

	Bank 0	0x0E	ISFR1	EXIF5	TCIF2	ADIF	0	EXIF3	TCIF4	SPIF	TCIF3
	Bank 0	0x0E	ISFR1	R/W	R/W	R/W	--	R/W	R/W	R/W	R/W
				R/W	R/W	R/W	--	R/W	R/W	R/W	R/W

	SFR	0x0E	IMR1	EXIE5	TCIE2	ADIE	0	EXIE3	TCIE4	SPIE	TCIE3
	SFR	0x0E	IMR1	R/W	R/W	R/W	--	R/W	R/W	R/W	R/W
				R/W	R/W	R/W	--	R/W	R/W	R/W	R/W

DCOL		RBFI	RBF		SE
		Set to 1			Clear
Collision					Clear
Collision		Buffer Full		Tx Empty
Detector		Detector		Tx Empty
					Detector
				SHIFT Register
				SPID			reg
				(8	bits)
SDI						SMP	TLS0~1
					DORD		TLS0~1
					DORD		2
							2
SDO
						Master/Slave
							EDS
		BRS2~0					Edge
		BRS2~0					Select
		3
/SS	/SS enable		BRS2~0
			BRS2~0	3
				3			SE
							SE
		Prescaler
Tsystem	4, 16, 64, 256,1024				Edge
					Select
	TC1/2					EDS		SCK
	TC1/2					EDS

Fig. 5-13 SPI Block Diagram

The serial interface are connected to external devices via P70 (/SCK), P71 (SI), P72 (SO). The serial interface can also be used as I/O port. In the transmit mode, P71 can be used as normal I/O port and in receive mode, P72 and P71 can be used as normal I/O ports.

Product Specification (V1.0) 10.03.2006

• 31

(This specification is subject to change without further notice)

Image 35

Contents DOC. Version EM78P312NElan Microelectronics Corporation Contents 16.3 14.116.1 16.2Bit Microcontroller General DescriptionPin Description Symbol Pin No Type FunctionFunction Description Functional Block DiagramOperating Registers Operating RegistersR2 Program Counter & Stack Bit Microcontroller R0 Indirect Addressing RegisterR1 Time Clock /Counter RBS1 RBS0 User Memory SpaceR3 Status Register Bit 7 ~ Bit 6 RBS1 ~ RBS0 R-Register page selectR5 System Control Register Bit 1 SIS Sleep and Idle mode selectSIS = 0 Idle mode SIS = 1 Sleep mode Bit 0 C Carry flag R4 RAM Select RegisterR7 Port 7 I/O Data Register RB Timer/Counter 4 Control RegisterBit Microcontroller R6 Port 6 I/O Data Register Bit 7 ~ Bit 0 P67 ~ P60 8-bit Port 6 I/O data registerFosc=8M RC Timer 4 Data BufferClock Source Resolution Max. Time TC4CK2 TC4CK1 TC4CK0RFInterrupt Status Flag Register Bit Microcontroller RE Interrupt Status Flag RegisterBit 7 TC3CAP Software capture control Bank 1 R5 TC3CR Timer/Counter 3 Control RegisterTC3M = 1 Capture mode Bank 1 R6 TC3DA Timer 3 Data Buffer a Bank 1 R7 TC3DB Timer 3 Data Buffer BBank 1 RB Adcr AD Control Register Bank 1 R9 TC2DH Timer 2 Data Buffer High ByteBank 1 RA TC2DL Timer 2 Data Buffer Low Byte TC2S = 0 Stop and counter clearBank 1 RD Addh AD High 8-bit Data Buffer Bit 7 ~ Bit 0 ADE7 ~ ADE0 AD input pin enable controlBit 5~ Bit 4 ADCK1 ~ ADCK0 AD Conversion Time Select Bank 1 RC Adic AD Input Pin ControlBit TEN = 0 Disable TEN = 1 EnableBit Microcontroller Bank 1 RE Tbktc TBT/Keytone Control Bank 2 R5 URC1 Uart Control RegisterTC2CK1 TC2CK0 Bank 2 R7 URS Uart Status RegisterBit 7 URRD8 Receiving data Bit BRATE2 BRATE1 BRATE0Bank 2 R9 Urtd Uart Transmit Data Buffer Bit 5 PRE Enable parity additionBit 6 Even Select parity check Even = 0 Odd parity Even = 1 Even parityBit 0 WBE Write buffer empty flag. Read only Bit 5 ~ Bit 3 BRS0 ~ BRS2 SPI Clock Source SelectBit 2 EDS Data shift out edge select EDS = 0 Rising edge EDS = 1 Falling edgeSPID7 SPID6 SPID5 SPID4 SPID3 SPID2 SPID1 SPID0 PHE6x = 1 Disable P6x pull highTransfer Mode Bank 3 RB PLC1 Pull Low Control RegisterSpecial Purpose Registers TC2ES = 0 Rising edge TC2ES = 1 Falling edge IOC6 ~ IOC9 − I/O Port Control RegisterIntcr − INT Control Register Address 0Bh INT1ES = 0 Rising edge INT1ES = 1 Falling edgeCali Sign External InterruptAdoscr − AD Offset Control Register Address 0Ch Uerrie Urie Utie Tbie EXIE1 TCIE0 IMR2 − Interrupt Mask Register 2 Address 0FhOperation Mode CPU Operation ModeRegisters for CPU Operation Mode Mode Switching ControlWake-up Methods Sleep Mode Idle ModeWake-up Signal R5 SIS = 1+SLEP R5 SIS= 0 + Slep Instruction AD ConverterConversion Time Operation Mode Max. Frequency Max. Conversion Rate per BitADC Data Register Sampling TimeAddress Name Bit Time Base Timer and Keytone GeneratorMUX Name Bit Uart Universal Asynchronous Receiver/TransmitterRegisters for Uart Circuit Transmitting Uart ModeBaud Rate Generator ReceivingRbank Address Name Bit SPI Serial Peripheral InterfaceRegisters for the SPI Circuit Serial Clock Shift Direction and Sample PhaseTransfer Mode Bit Transmit ModeSCK pin Bit Microcontroller Bit Receive ModeBit Transmit/Receive Mode Multiple Device Connect /SS SpisRegisters for Timer/Counter 2 Circuit Timer/CounterWindow Mode Timer ModeCounter Mode 21 Window Mode Timing Chart Registers for Timer/Counter 3 Circuit22 Configuration of Timer/Counter3 Capture ModeTCIF4 Registers for Timer 4 CircuitTCR4 PDO ModeTC4 Interrupt PWM Mode12 TCC/WDT & Prescaler Up-counter13 I/O Ports Reset and Wake-upReset Wake-up from Idle Mode Wake-up from Sleep ModeSummary of the Initialized Values for Registers Address Name Reset Type BitSCR Bit Microcontroller Register BankAddres URTD8 Events that may affect the T and P Status Reset TypeStatus of RST, T, and P of the Status Register Bit Microcontroller General Purpose RegistersInterrupt 28 Controller Reset Block DiagramSummary of Maximum Operating Speeds OscillatorOscillator Modes Crystal Oscillator/Ceramic Resonators Crystal740 EM78P312N 809N Oscillator Type Frequency Mode Frequency C1 pF C2 pFOS CI External RC Oscillator ModeBit 12 ~ 9 Not used Enwdtb = 0 Enable Enwdtb = 1 DisableCode Option Register Code Option Register WordOSC = 0 RC type OSC = 1 Crystal type Power-on ConsiderationsExternal Power-on Reset Circuit Customer ID RegisterEM78P809N Residue-Voltage ProtectionVdd EM78P312NBinary Instruction Hex Mnemonic Operation Status Instruction SetDEC Binary Instruction Hex Mnemonic Operation Status AffectedVss = Symbol Parameter Condition Min Typ Max UnitAbsolute Maximum Ratings Recommended Operating ConditionsTa= 25 C, VDD= 5.0V ± 5%, VSS= DC Electrical CharacteristicsTa= 25 C, VDD= 3.0V ± 5%, VSS= Varef Ta=- 40C ~ 85 C, VDD=5V ± 5%, VSS=0V AC Electrical CharacteristicSymbol Parameter Conditions Min Typ Max Unit AC Test Input/Output Waveform Timing DiagramEM78P311SxY OTP MCUPackage Type Pin Count Package Size