IBM EM78P312N manual Interrupt, Controller Reset Block Diagram

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EM78P312N

8-Bit Microcontroller

	VDD
Oscillator	D	Q	CLK
	CLK		CLK
	CLK
	CLR
Power-on
Reset
Voltage
Detector
WDTE
WDT	WDT Timeout	Setup Time	RESET
WDT		Setup Time	RESET
/RESET

Fig. 5-28 Controller Reset Block Diagram

5.15 Interrupt

The EM78P312N has 15 interrupts (9 external, 6 internal) as listed below:

Table 9 Interrupt Vector

Interrupt Source

Enable Condition

Int. Flag

Int. Vector Priority

	Internal /	Reset	−	−	0000	High 0
	External	Reset	−	−	0000	High 0
	External
	Internal	WDT	ENI + WDTEN	WDTIF	0003	1
	External	INT0	ENI + INT0EN=1	EXIEF0	0006	2
	Internal	TCC	ENI + TCIE0=1	TCIF0	0009	3
	External	INT1	ENI + EXIE1=1	EXIF1	000F	4
	Internal	TBT	ENI + TBIE=1	TBIF	0012	5
	Internal	UART Transmit	ENI + UTIE=1	TBEF	0015	6
	Internal	UART Receive	ENI + URIE=1	TBFF	0018	7
	Internal	UART Receive error	ENI+UERRIE=1	UERRIF	001B	8
	Internal	TC3	ENI + TCIE3=1	TCIF3	0021	9
	Internal	SPI	ENI + SPIE=1	SPIF	0024	10

	Internal	TC4	ENI + TCIE4=1	TCIF4	0027	11
	External	INT3	ENI + EXIE3=1	EXIF3	002A	12

	Internal	AD	ENI + ADIE=1	ADIF	0030	13
	Internal	TC2	ENI + TCIE2=1	TCIF2	0033	14

	External	INT5	ENI + EXIE5=1	EXIF5	0036	Low 15

ISFR0, ISFR1 and ISFR2 are the interrupt status registers that record the interrupt requests in the relative flags/bits. IMR1 and IMR2 are the interrupt mask registers. The global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. When one of the interrupts (enabled) occurs, the next instruction will be fetched from individual address. The interrupt flag bit must be cleared by instructions before leaving the interrupt service routine and before interrupts are enabled to avoid recursive interrupts.

Product Specification (V1.0) 10.03.2006

• 49

(This specification is subject to change without further notice)

Image 53

Contents DOC. Version EM78P312NElan Microelectronics Corporation Contents 16.1 14.116.2 16.3Bit Microcontroller General DescriptionPin Description Symbol Pin No Type FunctionFunction Description Functional Block DiagramOperating Registers Operating RegistersR2 Program Counter & Stack Bit Microcontroller R0 Indirect Addressing RegisterR1 Time Clock /Counter R3 Status Register User Memory SpaceBit 7 ~ Bit 6 RBS1 ~ RBS0 R-Register page select RBS1 RBS0SIS = 0 Idle mode SIS = 1 Sleep mode Bit 1 SIS Sleep and Idle mode selectBit 0 C Carry flag R4 RAM Select Register R5 System Control RegisterBit Microcontroller R6 Port 6 I/O Data Register RB Timer/Counter 4 Control RegisterBit 7 ~ Bit 0 P67 ~ P60 8-bit Port 6 I/O data register R7 Port 7 I/O Data RegisterClock Source Resolution Max. Time RC Timer 4 Data BufferTC4CK2 TC4CK1 TC4CK0 Fosc=8MRFInterrupt Status Flag Register Bit Microcontroller RE Interrupt Status Flag RegisterTC3M = 1 Capture mode Bank 1 R6 TC3DA Timer 3 Data Buffer a Bank 1 R5 TC3CR Timer/Counter 3 Control RegisterBank 1 R7 TC3DB Timer 3 Data Buffer B Bit 7 TC3CAP Software capture controlBank 1 RA TC2DL Timer 2 Data Buffer Low Byte Bank 1 R9 TC2DH Timer 2 Data Buffer High ByteTC2S = 0 Stop and counter clear Bank 1 RB Adcr AD Control RegisterBit 5~ Bit 4 ADCK1 ~ ADCK0 AD Conversion Time Select Bit 7 ~ Bit 0 ADE7 ~ ADE0 AD input pin enable controlBank 1 RC Adic AD Input Pin Control Bank 1 RD Addh AD High 8-bit Data BufferBit Microcontroller Bank 1 RE Tbktc TBT/Keytone Control TEN = 0 Disable TEN = 1 EnableBank 2 R5 URC1 Uart Control Register BitBit 7 URRD8 Receiving data Bit Bank 2 R7 URS Uart Status RegisterBRATE2 BRATE1 BRATE0 TC2CK1 TC2CK0Bit 6 Even Select parity check Bit 5 PRE Enable parity additionEven = 0 Odd parity Even = 1 Even parity Bank 2 R9 Urtd Uart Transmit Data BufferBit 2 EDS Data shift out edge select Bit 5 ~ Bit 3 BRS0 ~ BRS2 SPI Clock Source SelectEDS = 0 Rising edge EDS = 1 Falling edge Bit 0 WBE Write buffer empty flag. Read onlyTransfer Mode PHE6x = 1 Disable P6x pull highBank 3 RB PLC1 Pull Low Control Register SPID7 SPID6 SPID5 SPID4 SPID3 SPID2 SPID1 SPID0Special Purpose Registers Intcr − INT Control Register Address 0Bh IOC6 ~ IOC9 − I/O Port Control RegisterINT1ES = 0 Rising edge INT1ES = 1 Falling edge TC2ES = 0 Rising edge TC2ES = 1 Falling edgeCali Sign External InterruptAdoscr − AD Offset Control Register Address 0Ch Uerrie Urie Utie Tbie EXIE1 TCIE0 IMR2 − Interrupt Mask Register 2 Address 0FhRegisters for CPU Operation Mode CPU Operation ModeMode Switching Control Operation ModeWake-up Signal R5 SIS = 1+SLEP R5 SIS= 0 + Slep Instruction Sleep Mode Idle ModeAD Converter Wake-up MethodsADC Data Register Operation Mode Max. Frequency Max. Conversion Rate per BitSampling Time Conversion TimeAddress Name Bit Time Base Timer and Keytone GeneratorMUX Name Bit Uart Universal Asynchronous Receiver/TransmitterRegisters for Uart Circuit Transmitting Uart ModeBaud Rate Generator ReceivingRbank Address Name Bit SPI Serial Peripheral InterfaceRegisters for the SPI Circuit Transfer Mode Shift Direction and Sample PhaseBit Transmit Mode Serial ClockSCK pin Bit Microcontroller Bit Receive ModeBit Transmit/Receive Mode Multiple Device Connect /SS SpisRegisters for Timer/Counter 2 Circuit Timer/CounterWindow Mode Timer ModeCounter Mode 21 Window Mode Timing Chart Registers for Timer/Counter 3 Circuit22 Configuration of Timer/Counter3 Capture ModeTCIF4 Registers for Timer 4 CircuitTCR4 PDO Mode12 TCC/WDT & Prescaler PWM ModeUp-counter TC4 Interrupt13 I/O Ports Reset and Wake-upReset Wake-up from Idle Mode Wake-up from Sleep ModeSummary of the Initialized Values for Registers Address Name Reset Type BitSCR Bit Microcontroller Register BankAddres URTD8 Status of RST, T, and P of the Status Register Reset TypeBit Microcontroller General Purpose Registers Events that may affect the T and P StatusInterrupt 28 Controller Reset Block DiagramOscillator Modes OscillatorCrystal Oscillator/Ceramic Resonators Crystal Summary of Maximum Operating Speeds740 EM78P312N 809N Oscillator Type Frequency Mode Frequency C1 pF C2 pFOS CI External RC Oscillator ModeCode Option Register Enwdtb = 0 Enable Enwdtb = 1 DisableCode Option Register Word Bit 12 ~ 9 Not usedExternal Power-on Reset Circuit Power-on ConsiderationsCustomer ID Register OSC = 0 RC type OSC = 1 Crystal typeVdd Residue-Voltage ProtectionEM78P312N EM78P809NBinary Instruction Hex Mnemonic Operation Status Instruction SetDEC Binary Instruction Hex Mnemonic Operation Status AffectedAbsolute Maximum Ratings Symbol Parameter Condition Min Typ Max UnitRecommended Operating Conditions Vss =Ta= 25 C, VDD= 5.0V ± 5%, VSS= DC Electrical CharacteristicsTa= 25 C, VDD= 3.0V ± 5%, VSS= Varef Ta=- 40C ~ 85 C, VDD=5V ± 5%, VSS=0V AC Electrical CharacteristicSymbol Parameter Conditions Min Typ Max Unit AC Test Input/Output Waveform Timing DiagramPackage Type OTP MCUPin Count Package Size EM78P311SxY