IBM EM78P312N manual Addres

Page 50

EM78P312N

8-Bit Microcontroller

Register Bank 1

Addres

 

Name

Reset Type

 

Bit 7

 

Bit 6

 

Bit 5

 

Bit 4

 

Bit 3

 

Bit 2

 

Bit 1

 

Bit 0

s

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit Name

 

TC3CAP

 

TC3S

 

TC3CK1

 

TC3CK0

 

TC3M

 

X

 

X

 

X

0x05

 

TC3CR

Power-on

 

0

 

0

 

0

 

0

 

0

 

U

 

U

 

U

 

/RESET and WDT time out

 

0

 

0

 

0

 

0

 

0

 

U

 

U

 

U

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Wake-up from Sleep, Idle mode

 

P

 

P

 

P

 

P

 

P

 

U

 

U

 

U

 

 

 

Bit Name

 

TC3DA7

 

TC3DA6

 

TC3DA5

 

TC3DA4

 

TC3DA3

 

TC3DA2

 

TC3DA1

 

TC3DA0

0x06

 

TC3DA

Power-on

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

/RESET and WDT time out

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Wake-up from Sleep, Idle mode

 

P

 

P

 

P

 

P

 

P

 

P

 

P

 

P

 

 

 

Bit Name

 

TC3DB7

 

TC3DB6

 

TC3DB5

 

TC3DB4

 

TC3DB3

 

TC3DB2

 

TC3DB1

 

TC3DB0

0x07

 

TC3DB

Power-on

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

/RESET and WDT time out

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Wake-up from Sleep, Idle mode

 

P

 

P

 

P

 

P

 

P

 

P

 

P

 

P

 

 

 

Bit Name

 

ADD1

 

ADD0

 

X

 

TC2M

 

TC2S

 

TC2CK2

 

TC2CK1

 

TC2CK0

0x08

 

TC2CR/

Power-on

 

U

 

U

 

U

 

0

 

0

 

0

 

0

 

0

 

ADDL

/RESET and WDT time out

 

P

 

P

 

U

 

0

 

0

 

0

 

0

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

Wake-up from Sleep, Idle mode

 

P

 

P

 

U

 

P

 

0

 

P

 

P

 

P

 

 

 

Bit Name

 

TC2D15

 

TC2D14

 

TC2D13

 

TC2D12

 

TC2D11

 

TC2D10

 

TC2D9

 

TC2D8

0x09

 

TC2DH

Power-On

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

/RESET and WDT time out

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Wake-up from Sleep, Idle mode

 

P

 

P

 

P

 

P

 

P

 

P

 

P

 

P

 

 

 

Bit Name

 

TC2D7

 

TC2D6

 

TC2D5

 

TC2D4

 

TC2D3

 

TC2D2

 

TC2D1

 

TC2D0

0x0A

 

TC2DL

Power-on

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

/RESET and WDT time out

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Wake-up from Sleep, Idle mode

 

P

 

P

 

P

 

P

 

P

 

P

 

P

 

P

 

 

 

Bit Name

 

ADREF

 

ADRUN

 

ADCK1

 

ADCK0

 

ADP

 

ADIS2

 

ADIS1

 

ADIS0

0x0B

 

ADCR

Power-on

 

0

 

0

 

0

 

0

 

1

 

0

 

0

 

0

 

/RESET and WDT time out

 

0

 

0

 

0

 

0

 

1

 

0

 

0

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Wake-up from Sleep, Idle mode

 

P

 

(*)

 

P

 

P

 

P

 

P

 

P

 

P

 

 

 

Bit Name

 

ADE7

 

ADE6

 

ADE5

 

ADE4

 

ADE3

 

ADE2

 

ADE1

 

ADE0

0x0C

 

ADIC

Power-on

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

/RESET and WDT time out

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Wake-up from Sleep, Idle mode

 

P

 

P

 

P

 

P

 

P

 

P

 

P

 

P

 

 

 

Bit Name

 

ADD9

 

ADD8

 

ADD7

 

ADD6

 

ADD5

 

ADD4

 

ADD3

 

ADD2

0X0D

 

ADDH

Power-on

 

U

 

U

 

U

 

U

 

U

 

U

 

U

 

U

 

/RESET and WDT time out

 

P

 

P

 

P

 

P

 

P

 

P

 

P

 

P

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Wake-up from Sleep, Idle mode

 

P

 

P

 

P

 

P

 

P

 

P

 

P

 

P

 

 

 

Bit Name

 

TEN

 

TCK1

 

TCK0

 

X

 

TBTEN

 

TBTCK2

 

TBTCK1

 

TBTCK0

0X0E

 

TBKTC

Power-on

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

/RESET and WDT time out

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Wake-up from Sleep, Idle mode

 

0

 

P

 

P

 

P

 

0

 

P

 

P

 

P

46

Product Specification (V1.0) 10.03.2006

(This specification is subject to change without further notice)

Image 50
Contents EM78P312N DOC. VersionElan Microelectronics Corporation Contents 16.2 14.116.1 16.3General Description Bit MicrocontrollerSymbol Pin No Type Function Pin DescriptionFunctional Block Diagram Function DescriptionOperating Registers Operating RegistersR2 Program Counter & Stack Bit Microcontroller R0 Indirect Addressing RegisterR1 Time Clock /Counter Bit 7 ~ Bit 6 RBS1 ~ RBS0 R-Register page select User Memory SpaceR3 Status Register RBS1 RBS0Bit 0 C Carry flag R4 RAM Select Register Bit 1 SIS Sleep and Idle mode selectSIS = 0 Idle mode SIS = 1 Sleep mode R5 System Control RegisterBit 7 ~ Bit 0 P67 ~ P60 8-bit Port 6 I/O data register RB Timer/Counter 4 Control RegisterBit Microcontroller R6 Port 6 I/O Data Register R7 Port 7 I/O Data RegisterTC4CK2 TC4CK1 TC4CK0 RC Timer 4 Data BufferClock Source Resolution Max. Time Fosc=8MBit Microcontroller RE Interrupt Status Flag Register RFInterrupt Status Flag RegisterBank 1 R7 TC3DB Timer 3 Data Buffer B Bank 1 R5 TC3CR Timer/Counter 3 Control RegisterTC3M = 1 Capture mode Bank 1 R6 TC3DA Timer 3 Data Buffer a Bit 7 TC3CAP Software capture controlTC2S = 0 Stop and counter clear Bank 1 R9 TC2DH Timer 2 Data Buffer High ByteBank 1 RA TC2DL Timer 2 Data Buffer Low Byte Bank 1 RB Adcr AD Control RegisterBank 1 RC Adic AD Input Pin Control Bit 7 ~ Bit 0 ADE7 ~ ADE0 AD input pin enable controlBit 5~ Bit 4 ADCK1 ~ ADCK0 AD Conversion Time Select Bank 1 RD Addh AD High 8-bit Data BufferBank 2 R5 URC1 Uart Control Register TEN = 0 Disable TEN = 1 EnableBit Microcontroller Bank 1 RE Tbktc TBT/Keytone Control BitBRATE2 BRATE1 BRATE0 Bank 2 R7 URS Uart Status RegisterBit 7 URRD8 Receiving data Bit TC2CK1 TC2CK0Even = 0 Odd parity Even = 1 Even parity Bit 5 PRE Enable parity additionBit 6 Even Select parity check Bank 2 R9 Urtd Uart Transmit Data BufferEDS = 0 Rising edge EDS = 1 Falling edge Bit 5 ~ Bit 3 BRS0 ~ BRS2 SPI Clock Source SelectBit 2 EDS Data shift out edge select Bit 0 WBE Write buffer empty flag. Read onlyBank 3 RB PLC1 Pull Low Control Register PHE6x = 1 Disable P6x pull highTransfer Mode SPID7 SPID6 SPID5 SPID4 SPID3 SPID2 SPID1 SPID0Special Purpose Registers INT1ES = 0 Rising edge INT1ES = 1 Falling edge IOC6 ~ IOC9 − I/O Port Control RegisterIntcr − INT Control Register Address 0Bh TC2ES = 0 Rising edge TC2ES = 1 Falling edgeCali Sign External InterruptAdoscr − AD Offset Control Register Address 0Ch IMR2 − Interrupt Mask Register 2 Address 0Fh Uerrie Urie Utie Tbie EXIE1 TCIE0Mode Switching Control CPU Operation ModeRegisters for CPU Operation Mode Operation ModeAD Converter Sleep Mode Idle ModeWake-up Signal R5 SIS = 1+SLEP R5 SIS= 0 + Slep Instruction Wake-up MethodsSampling Time Operation Mode Max. Frequency Max. Conversion Rate per BitADC Data Register Conversion TimeTime Base Timer and Keytone Generator Address Name BitMUX Name Bit Uart Universal Asynchronous Receiver/TransmitterRegisters for Uart Circuit Uart Mode TransmittingReceiving Baud Rate GeneratorRbank Address Name Bit SPI Serial Peripheral InterfaceRegisters for the SPI Circuit Bit Transmit Mode Shift Direction and Sample PhaseTransfer Mode Serial ClockSCK pin Bit Microcontroller Bit Receive ModeBit Transmit/Receive Mode Spis Multiple Device Connect /SSTimer/Counter Registers for Timer/Counter 2 CircuitWindow Mode Timer ModeCounter Mode Registers for Timer/Counter 3 Circuit 21 Window Mode Timing ChartCapture Mode 22 Configuration of Timer/Counter3Registers for Timer 4 Circuit TCIF4PDO Mode TCR4Up-counter PWM Mode12 TCC/WDT & Prescaler TC4 Interrupt13 I/O Ports Reset and Wake-upReset Wake-up from Sleep Mode Wake-up from Idle ModeAddress Name Reset Type Bit Summary of the Initialized Values for RegistersBit Microcontroller Register Bank SCRAddres URTD8 Bit Microcontroller General Purpose Registers Reset TypeStatus of RST, T, and P of the Status Register Events that may affect the T and P Status28 Controller Reset Block Diagram InterruptCrystal Oscillator/Ceramic Resonators Crystal OscillatorOscillator Modes Summary of Maximum Operating SpeedsOscillator Type Frequency Mode Frequency C1 pF C2 pF 740 EM78P312N 809NExternal RC Oscillator Mode OS CICode Option Register Word Enwdtb = 0 Enable Enwdtb = 1 DisableCode Option Register Bit 12 ~ 9 Not usedCustomer ID Register Power-on ConsiderationsExternal Power-on Reset Circuit OSC = 0 RC type OSC = 1 Crystal typeEM78P312N Residue-Voltage ProtectionVdd EM78P809NInstruction Set Binary Instruction Hex Mnemonic Operation StatusBinary Instruction Hex Mnemonic Operation Status Affected DECRecommended Operating Conditions Symbol Parameter Condition Min Typ Max UnitAbsolute Maximum Ratings Vss =DC Electrical Characteristics Ta= 25 C, VDD= 5.0V ± 5%, VSS=Ta= 25 C, VDD= 3.0V ± 5%, VSS= Varef Ta=- 40C ~ 85 C, VDD=5V ± 5%, VSS=0V AC Electrical CharacteristicSymbol Parameter Conditions Min Typ Max Unit Timing Diagram AC Test Input/Output WaveformPin Count Package Size OTP MCUPackage Type EM78P311SxY