EM78P312N
8-Bit Microcontroller
of the TC3 pin input, the contents of the counter are loaded into TCR3A, counter is cleared and interrupt is generated again. If an overflow before the edge is detected, the FFH is loaded into TCR3DA and an overflow interrupt is generated. During interrupt processing, it can be determined whether or not there is an overflow by checking whether the TCR3DA value is FFH. After an interrupt (capture to TCR3DA or overflow detection) is generated, capture and overflow detection are halted until TCR3DA is read out.
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| K 0 1 | m+1 | n 0 1 2 | 3 | FE FF0 1 | 2 3 |
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| TC3 Pin Input |
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| TCR3DA | K |
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| FF (Overflow) |
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| TCR3DB |
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| FE |
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| TC3 Interrupt | Capture |
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| Capture |
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| Overflow |
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| Reading TCR3DA |
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| Fig. |
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5.11 Timer/Counter 4 |
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| Registers for Timer 4 Circuit |
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R_BANK | Address | Name |
| Bit 7 | Bit 6 |
| Bit 5 |
| Bit 4 |
| Bit 3 | Bit 2 |
| Bit 1 | Bit 0 |
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Bank 0 |
| 0X0B | TC4CR |
| TC4FF1 | TC4FF0 |
| TC4S |
| TC4CK2 | TC4CK1 | TC4CK0 |
| TC4M1 | TC4M0 |
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| R/W |
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| R/W | R/W |
| R/W | R/W |
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Bank 0 |
| 0X0C | TC4D |
| TC4D7 | TC4D6 |
| TC4D5 |
| TC4D4 | TC4D3 | TC4D2 |
| TC4D1 | TC4D0 |
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| R/W |
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| R/W | R/W |
| R/W | R/W |
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Bank 0 |
| 0x0E | ISFR1 |
| EXIF5 | TCIF2 |
| ADIF |
| 0 |
| EXIF3 | TCIF4 |
| SPIF | TCIF3 |
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| R/W |
| R/W |
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| R/W | R/W |
| R/W | R/W |
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| SFR |
| 0x0E | IMR1 |
| EXIE5 | TCIE2 |
| ADIE |
| 0 |
| EXIE3 | TCIE4 |
| SPIE | TCIE3 |
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| R/W |
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| R/W | R/W |
| R/W | R/W |
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Product Specification (V1.0) 10.03.2006 | • 39 |
(This specification is subject to change without further notice)