disable(); | /* disable all interrupt */ | ||||
outportb(wBase+5,0); | |||||
if (wIrq<8) |
|
|
|
| |
| { |
|
|
|
|
| irqmask=inportb(A1_8259+1); |
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|
|
| outportb(A1_8259+1,irqmask & 0xff ^ (1<<wIrq)); |
|
| ||
| setvect(wIrq+8,irq_service); |
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|
|
| } |
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else |
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|
| |
| { |
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|
|
| irqmask=inportb(A1_8259+1); |
|
| /* IRQ2 */ | |
| outportb(A1_8259+1,irqmask & 0xfb); |
| |||
| irqmask=inportb(A2_8259+1); |
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|
| outportb(A2_8259+1,irqmask & 0xff ^ |
| |||
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|
| ||
| } |
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|
|
invert=0x05; | /* P2C0 = | ||||
outportb(wBase+0x2a,invert); | |||||
|
| /* P5C0 | = | inverte input */ | |
|
| /* P8C0 = | |||
|
| /* P11C0 = | inverte input */ | ||
now_int_state=0x0a; | /* P2C0 | = Low |
| */ | |
|
| /* P5C0 | = High |
| */ |
|
| /* P8C0 | = Low |
| */ |
|
| /* P11C0 = High |
| */ | |
CNT_L1=CNT_L2=CNT_L3=CNT_L4=0; | /* Low_pulse counter | */ | |||
CNT_H1=CNT_H2=CNT_H3=CNT_H4=0; | /* High_pulse counter | */ | |||
int_num=0; | /* enable interrupt P2C0 | */ | |||
outportb(wBase+5,0x0f); | |||||
enable(); | /* P5C0, P8C0, P11C0 | */ | |||
} |
|
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|
|
|
/* |
|
| */ | ||
/* NOTE:1.The | */ | ||||
/* | 2.The ISR must read the interrupt status again to the | */ | |||
/* | active interrupt sources. |
|
| */ | |
/* | 3.The INT_CHAN_0&INT_CHAN_1 can be active at the same time*/ | ||||
/* |
|
| */ | ||
void interrupt irq_service() |
|
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| |
{ |
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|
int_num++; |
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|
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| |
new_int_state=inportb(wBase+7)&0x0f; |
|
|
| ||
int_c=new_int_state^now_int_state; |
|
|
| ||
if ((int_c&0x1)!=0) |
|
|
|
| |
| { | /* now P2C0 change to high | */ | ||
| if ((new_int_state&0x01)!=0) | ||||
| { |
|
|
|
|
| CNT_H1++; |
|
|
|
|
| } | /* now P2C0 change to low | */ | ||
| else | ||||
| { |
|
|
|
|
| CNT_L1++; |
|
|
|
|
| } | /* generate a high pulse | */ | ||
| invert=invert^1; | ||||
| } |
|
|
|
|
if ((int_c&0x2)!=0) |
|
|
|
| |
| { | /* now P5C0 change to high | */ | ||
| if ((new_int_state&0x02)!=0) | ||||
| { |
|
|
|
|
| CNT_H2++; |
|
|
|
|
| } |
|
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| ||||