Omega Engineering OME-PIO-D96 RESET\ Control Register, AUX Control Register, AUX data Register

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3.3.1RESET\ Control Register

(Read/Write): wBase+0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved Reserved Reserved Reserved Reserved Reserved Reserved RESET\

Note. Refer to Sec. 3.1 for more information about wBase.

When the PC is first power-on, the RESET\ signal is in Low-state. This will disable all D/I/O operations. The user has to set the RESET\ signal to High-state before any D/I/O command.

outportb(wBase,1);	/*	RESET\=High Æ all D/I/O are enable now */
outportb(wBase,0);	/*	RESET\=Low Æ all D/I/O are disable now */

3.3.2AUX Control Register

(Read/Write): wBase+2

Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
Aux7	Aux6	Aux5	Aux4	Aux3	Aux2	Aux1	Aux0

Note. Refer to Sec. 3.1 for more information about wBase.

Aux?=0Æ this Aux is used as a D/I Aux?=1Æ this Aux is used as a D/O

When the PC is first power-up, All Aux? signal are in Low-state. All Aux? are designed as D/I for all PIO/PISO series. Please set all Aux? in D/I state.

3.3.3AUX data Register

(Read/Write): wBase+3

Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
Aux7	Aux6	Aux5	Aux4	Aux3	Aux2	Aux1	Aux0

Note. Refer to Sec. 3.1 for more information about wBase.

When the Aux? is used as D/O, the output state is controlled by this register. This register is designed for feature extension, so don’t control this register now.

OME-PIO-D96 User Manual (Ver.1.1, Mar/2003)

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Contents User’sGuide Mexico CanadaBenelux Czech RepublicOME-PIO-D96 Table of Contents Introduction FeaturesSpecifications Order DescriptionOptions PCI Data Acquisition Family Product Check ListOME-PISO-series cost-effective generation, isolated cards Board Layout Hardware configurationEnable I/O Operation I/O port LocationRefer to DEMO1.C for demo program D/I/O Architecture Make sure the initial level is High or Low Interrupt OperationINTCHAN3 Interrupt Block Diagram of OME-PIO-D96INTCHAN0/1/2/3 COUNTL++ Initialhigh, activelow Interrupt sourceInitiallow, activehigh Interrupt source Muliti Interrupt Source Read all interrupt state OME-DB-37 Daughter BoardsOME-DN-37 & OME-DN-50 OME-DB-8125OME-ADP-37/PCI & OME-ADP-50/PCI OME-DB-24P/24PD Isolated Input Board OME-DB-24R/24RD Relay Board OME-DB-24PR/24POR/24C Daughter Boards Comparison Table Pin Assignment All signals are TTL compatibleVCC GND Resource-allocated information How to Find the I/O AddressOME-PIO/PISO identification information PC’s physical slot informationPIODriverInit PIODriverInit&wBoards, wSubVendor,wSubDevice,wSubAuxWSubVendor=0x80 wSubDevice=1 wSubAux=0x10 /* for PIOD96 Current sinking PIOGetConfigAddressSpace Enable all D/I/O operation of card0Enable all D/I/O operation of card1 ShowPIOPISOwSubVendor,wSubDevice,wSubAux ShowPIOPISOSlot5 0x0A Slot6 0x08 Slot7 0x09 Slot8 0x07 Assignment of I/O AddressAddress Read Write I/O Address MapRESET\ Control Register AUX Control RegisterAUX data Register Aux Status Register INT Mask Control RegisterINV3 INV2 INV1 INV0 Interrupt Polarity Control Register7 I/O Selection Control Register Read/Write 8-bit data Register Demo program How to install software & utility?Piopiso PIOPISO.EXE for Windows DEMO1 DEMO2 DEMO3 COUNTL++ DEMO4 COUNTL++ DEMO5 CNTL1=CNTL2=CNTL3=CNTL4=0 Page WARRANTY/DISCLAIMER Temperature