Cypress CY7C1382DV25, CY7C1380DV25, CY7C1380FV25 Soldernotespad Type NON-SOLDER Mask Defined Nsmd

Page 28

CY7C1380DV25, CY7C1380FV25

CY7C1382DV25, CY7C1382FV25

Package Diagrams (continued)

Figure 3. 165-Ball FBGA (13 x 15 x 1.4 mm) (51-085180)

165 FBGA 13 x 15 x 1.40 MM BB165D/BW165D

TOP VIEW

 

 

 

 

 

 

TOP VIEW

 

 

 

PIN 1 CORNER

 

 

 

 

 

 

 

 

 

 

PIN 1 CORNER

 

 

 

 

 

 

 

1

2

3

4

5

6

7

8

9

10

11

BOTTOM VIEW

BOTTOM VIEWPIN 1 CORNER

PIN 1 CORNER

 

 

 

 

 

Ø0.05 M C

 

 

 

 

 

 

 

 

 

 

Ø0.05 M C

 

 

 

 

 

 

 

Ø0.25 M C A B

 

 

 

 

 

 

 

Ø0.50

-0Ø0.06

.25 M C A B

 

 

 

 

 

(165X)

 

 

 

 

 

 

 

 

 

+0.14

-0.06

 

11

10

9

8

7

6

5

Ø0.50

(165X)

4

3

2

1

 

 

 

 

 

 

 

 

 

+0.14

 

15.00±0.10

15.00±0.10

A

1

2

3

4

5

6

7

8

9

10

11

B

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CB

DC

ED

FE

GF

H

G

15.00±0.10

 

 

 

J

H

 

K

J

 

 

 

LK

ML

NM

PN

RP R

14.00 15.00±0.10

1.00

7.0014.00

1.00

7.00

11

10

9

8

7

6

5

4

3

2

1A

BA

CB

DC

ED

FE

GF

HG

JH

KJ

LK

ML

NM

PN

RP

R

A

0.25 C

A

0.3600.25.3±0C .05

A

B

13.00±0.10

 

 

B

13.00±0.10

 

 

0.53±0.05

1.40 MAX.

0.15 C 1.40 MAX.

0.15 C

C

SEATING PLANE

 

 

SEATING PLANE

 

 

 

 

 

0.36

C

 

 

0.35±0.06

0.35±0.06

 

 

1.00

A

5.00

1.00

 

5.00

 

10.00

 

10.00

B

13.00±0.10

B

13.00±0.10

0.15(4X)

 

0.15(4X)

 

NOTES :

 

SOLDERNOTESPAD TYPE: : NON-SOLDER MASK DEFINED (NSMD)

PACKAGESOLDERW IGHTPAD: 0TYPE.475g: NON-SOLDER MASK DEFINED (NSMD)

JEDEC REFERENCEPACKAGE WEIGHT: MO-216: 0./475gDESIGN 4.6C

PACKAGEJEDECODEREFERENCE: BB0AC : MO-216 / DESIGN 4.6C

PACKAGE CODE : BB0AC

51-85180-*A

51-85180-*A

Intel and Pentium are registered trademarks, and i486 is a trademark of Intel Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.

Document #: 38-05546 Rev. *E

Page 28 of 29

© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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Contents Features Selection Guide250 MHz 200 MHz 167 MHz Unit Cypress Semiconductor CorporationLogic Block Diagram CY7C1380DV25/CY7C1380FV25 3 512K x Logic Block Diagram CY7C1382DV25/CY7C1382FV25 3 1M xCY7C1380DV25 512K X Pin Configurations Pin Tqfp Pinout 3 Chip EnableCY7C1382DV25 1M x Pin Configurations Ball BGA Pinout CY7C1380FV25 512K xPin Configurations Ball Fbga Pinout 3 Chip Enable CY7C1380DV25 512K xPower supply inputs to the core of the device Pin DefinitionsName Description Byte write select inputs, active LOW. Qualified withPower supply for the IO circuitry Single Read AccessesSingle Write Accesses Initiated by Adsp Functional OverviewInterleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Burst SequencesOperation Add. Used CE1 CE2 CE3 Adsp Adsc ADV Write CLKFunction CY7C1380DV25/CY7C1380FV25 Truth Table for Read/Write 6Function CY7C1382DV25/CY7C1382FV25 TAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag Bypass Register TAP Instruction SetTAP AC Switching Characteristics TAP TimingParameter Description Min Max Unit Clock Hold TimesTAP DC Electrical Characteristics And Operating Conditions 5V TAP AC Test Conditions5V TAP AC Output Load Equivalent Identification Register DefinitionsIdentification Codes Ball BGA Boundary Scan Order 13Instruction Code Description Bit # Ball IDA11 Maximum Ratings Electrical CharacteristicsOperating Range Capacitance Thermal ResistanceAC Test Loads and Waveforms PackageSwitching Characteristics Setup Times250 MHz 200 MHz 167 MHz Parameter Description Min Output TimesSwitching Waveforms Read Cycle TimingWrite Cycle Timing 25 Read/Write Cycle Timing 25, 27 CLZZZ Mode Timing 29 DON’T CareOrdering Information CY7C1382DV25-250BZXI Document # 38-05546 Rev. *E Package Diagrams Pin Thin Plastic Quad Flat pack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Orig. Description of Change DateDocument Number

CY7C1382DV25, CY7C1380DV25, CY7C1382FV25, CY7C1380FV25 specifications

The Cypress CY7C1380FV25, CY7C1382FV25, CY7C1380DV25, and CY7C1382DV25 are high-performance static random access memory (SRAM) devices distinguished by their reliability and efficiency. These components are designed for applications requiring fast data storage and retrieval, making them ideal for embedded systems, communication devices, and various consumer electronics.

One of the main features of these SRAMs is their access time. The CY7C1380FV25 and CY7C1382FV25 models come with a super-fast access time of 25 nanoseconds, ensuring that data can be retrieved with minimal delay. This characteristic is crucial for high-speed applications, such as networking equipment and automotive systems, where rapid data processing is essential.

Both families of devices offer a competitive data width configuration, with CY7C1380 series providing 8 bits and CY7C1382 series providing 16 bits. This flexibility allows designers to choose the appropriate configuration based on their specific application requirements. Additionally, they support a wide voltage range for ease of integration into various systems.

The CY7C1380FV25 and CY7C1380DV25 devices feature low power consumption, which is vital for battery-operated devices. With their advanced CMOS technology, they exhibit reduced static power requirements, helping to prolong battery life and improve overall system efficiency. The IDD (supply current) ratings are particularly low, making them suitable for energy-sensitive applications.

A notable characteristic of the Cypress memory devices is their asynchronous read and write operations, providing simple interfacing in a variety of designs. They are designed to operate under a wide range of temperature conditions; thus, they are well-suited for industrial applications where temperature fluctuations might be a concern.

Furthermore, the CY7C1382FV25 and CY7C1382DV25 models include features like burst mode capability, enabling faster sequential access, which is beneficial for high-speed data processing tasks. This allows these SRAMs to deliver enhanced performance critical in applications like video processing and real-time data acquisition.

In summary, the Cypress CY7C1380FV25, CY7C1382FV25, CY7C1380DV25, and CY7C1382DV25 are distinguished by their fast access times, low power consumption, and flexible data widths. Their advanced technologies and characteristics make them a reliable choice for a diverse range of high-performance applications, ensuring that engineers can effectively address their design challenges while meeting the demands of modern electronics.
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