Cypress CY7C1380FV25 manual Pin Definitions, Name Description, Ground for the core of the device

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CY7C1380DV25, CY7C1380FV25

Pin Definitions

 

 

 

 

 

CY7C1382DV25, CY7C1382FV25

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

IO

 

 

Description

 

 

 

 

 

A0, A1, A

Input-

Address inputs used to select one of the address locations. Sampled at the rising

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3[2]are sampled

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

active. A1: A0 are fed to the two-bit counter.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A,

 

 

 

 

Input-

Byte write select inputs, active LOW. Qualified with

 

to conduct byte writes to

 

BW

BW

B

BWE

 

BWC, BWD

Synchronous

the SRAM. Sampled on the rising edge of CLK.

 

 

 

 

 

 

 

 

 

 

Input-

Global write enable input, active LOW. When asserted LOW on the rising edge of

 

GW

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

CLK, a global write is conducted (all bytes are written, regardless of the values on BWX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

and BWE).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input-

Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal

 

BWE

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

must be asserted LOW to conduct a byte write.

 

 

 

 

 

CLK

Input-

Clock input. Used to capture all synchronous inputs to the device. Also used to

 

 

 

 

 

 

 

 

 

 

 

 

Clock

increment the burst counter when ADV is asserted LOW, during a burst operation.

 

 

 

 

 

 

 

 

 

 

1

 

 

 

Input-

Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in

 

CE

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

conjunction with CE2 and

CE

3 to select or deselect the device.

ADSP

is ignored if

CE

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

is HIGH. CE1 is sampled only when a new external address is loaded.

 

CE2 [2]

Input-

Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

conjunction with CE1 and CE3 to select or deselect the device. CE2 is sampled only

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

when a new external address is loaded.

 

 

 

 

 

 

 

3 [2]

Input-

Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in

 

CE

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

conjunction with CE1 and CE2 to select or deselect the device.

CE

3 is sampled only

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

when a new external address is loaded.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input-

Output enable, asynchronous input, active LOW. Controls the direction of the IO

 

OE

 

 

 

 

 

 

 

 

 

 

 

 

Asynchronous

pins. When LOW, the IO pins behave as outputs. When deasserted HIGH, IO pins are

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

when emerging from a deselected state.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input-

Advance input signal, sampled on the rising edge of CLK, active LOW. When

 

ADV

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

asserted, it automatically increments the address in a burst cycle.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input-

Address strobe from processor, sampled on the rising edge of CLK, active LOW.

 

ADSP

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

When asserted LOW, addresses presented to the device are captured in the address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HIGH.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input-

Address strobe from controller, sampled on the rising edge of CLK, active LOW.

 

ADSC

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

When asserted LOW, addresses presented to the device are captured in the address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

both asserted, only ADSP is recognized.

 

 

 

 

 

ZZ

Input-

ZZ sleep input. This active HIGH input places the device in a non-time critical sleep

 

 

 

 

 

 

 

 

 

 

 

 

Asynchronous

condition with data integrity preserved. For normal operation, this pin has to be LOW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

or left floating. ZZ pin has an internal pull down.

 

 

 

 

 

DQs, DQPX

IO-

Bidirectional data IO lines. As inputs, they feed into an on-chip data register that is

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

triggered by the rising edge of CLK. As outputs, they deliver the data contained in the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

memory location specified by the addresses presented during the previous clock rise

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

of the read cycle. The direction of the pins is controlled by OE. When OE is asserted

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

condition.

 

 

 

 

 

VDD

Power Supply

Power supply inputs to the core of the device.

 

VSS

Ground

Ground for the core of the device.

Document #: 38-05546 Rev. *E

 

 

 

 

 

 

 

 

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Contents 250 MHz 200 MHz 167 MHz Unit FeaturesSelection Guide Cypress Semiconductor CorporationLogic Block Diagram CY7C1380DV25/CY7C1380FV25 3 512K x Logic Block Diagram CY7C1382DV25/CY7C1382FV25 3 1M xPin Configurations Pin Tqfp Pinout 3 Chip Enable CY7C1380DV25 512K XCY7C1382DV25 1M x Pin Configurations Ball BGA Pinout CY7C1380FV25 512K xPin Configurations Ball Fbga Pinout 3 Chip Enable CY7C1380DV25 512K xName Description Power supply inputs to the core of the devicePin Definitions Byte write select inputs, active LOW. Qualified withSingle Write Accesses Initiated by Adsp Power supply for the IO circuitrySingle Read Accesses Functional OverviewZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Burst SequencesOperation Add. Used CE1 CE2 CE3 Adsp Adsc ADV Write CLKTruth Table for Read/Write 6 Function CY7C1380DV25/CY7C1380FV25Function CY7C1382DV25/CY7C1382FV25 TAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag Bypass Register TAP Instruction SetParameter Description Min Max Unit Clock TAP AC Switching CharacteristicsTAP Timing Hold Times5V TAP AC Output Load Equivalent TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions Identification Register DefinitionsInstruction Code Description Identification CodesBall BGA Boundary Scan Order 13 Bit # Ball IDA11 Electrical Characteristics Maximum RatingsOperating Range AC Test Loads and Waveforms CapacitanceThermal Resistance Package250 MHz 200 MHz 167 MHz Parameter Description Min Switching CharacteristicsSetup Times Output TimesSwitching Waveforms Read Cycle TimingWrite Cycle Timing 25 Read/Write Cycle Timing 25, 27 CLZZZ Mode Timing 29 DON’T CareOrdering Information CY7C1382DV25-250BZXI Document # 38-05546 Rev. *E Package Diagrams Pin Thin Plastic Quad Flat pack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Issue Orig. Description of Change Date Document HistoryDocument Number

CY7C1382DV25, CY7C1380DV25, CY7C1382FV25, CY7C1380FV25 specifications

The Cypress CY7C1380FV25, CY7C1382FV25, CY7C1380DV25, and CY7C1382DV25 are high-performance static random access memory (SRAM) devices distinguished by their reliability and efficiency. These components are designed for applications requiring fast data storage and retrieval, making them ideal for embedded systems, communication devices, and various consumer electronics.

One of the main features of these SRAMs is their access time. The CY7C1380FV25 and CY7C1382FV25 models come with a super-fast access time of 25 nanoseconds, ensuring that data can be retrieved with minimal delay. This characteristic is crucial for high-speed applications, such as networking equipment and automotive systems, where rapid data processing is essential.

Both families of devices offer a competitive data width configuration, with CY7C1380 series providing 8 bits and CY7C1382 series providing 16 bits. This flexibility allows designers to choose the appropriate configuration based on their specific application requirements. Additionally, they support a wide voltage range for ease of integration into various systems.

The CY7C1380FV25 and CY7C1380DV25 devices feature low power consumption, which is vital for battery-operated devices. With their advanced CMOS technology, they exhibit reduced static power requirements, helping to prolong battery life and improve overall system efficiency. The IDD (supply current) ratings are particularly low, making them suitable for energy-sensitive applications.

A notable characteristic of the Cypress memory devices is their asynchronous read and write operations, providing simple interfacing in a variety of designs. They are designed to operate under a wide range of temperature conditions; thus, they are well-suited for industrial applications where temperature fluctuations might be a concern.

Furthermore, the CY7C1382FV25 and CY7C1382DV25 models include features like burst mode capability, enabling faster sequential access, which is beneficial for high-speed data processing tasks. This allows these SRAMs to deliver enhanced performance critical in applications like video processing and real-time data acquisition.

In summary, the Cypress CY7C1380FV25, CY7C1382FV25, CY7C1380DV25, and CY7C1382DV25 are distinguished by their fast access times, low power consumption, and flexible data widths. Their advanced technologies and characteristics make them a reliable choice for a diverse range of high-performance applications, ensuring that engineers can effectively address their design challenges while meeting the demands of modern electronics.
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