Cypress CY7C1380DV25 Document History, Document Number, Issue Orig. Description of Change Date

Page 29

CY7C1380DV25, CY7C1380FV25

CY7C1382DV25, CY7C1382FV25

Document History Page

Document Title: CY7C1380DV25/CY7C1382DV25/CY7C1380FV25/CY7C1382FV25, 18-Mbit (512K x 36/1M x 18) Pipelined

SRAM

Document Number: 38-05546

REV.

ECN NO.

Issue

Orig. of

Description of Change

Date

Change

 

 

 

 

 

**

254515

See ECN

RKF

New data sheet

 

 

 

 

 

*A

288531

See ECN

SYT

Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for

 

 

 

 

non-compliance with 1149.1

 

 

 

 

Removed 225 and 133 Mhz Speed Bin

 

 

 

 

Added Pb-free information for 100-Pin TQFP, 119 BGA and 165 FBGA Packages

 

 

 

 

Added comment of ‘Pb-free BG packages availability’ below the Ordering Information

*B

326078

See ECN

PCI

Address expansion pins/balls in the pinouts for all packages are modified as per

 

 

 

 

JEDEC standard

 

 

 

 

Added description on EXTEST Outut Bus Tri-State

 

 

 

 

Changed description on the Tap Instruction Set Overview and Extest

 

 

 

 

Changed Device Width (23:18) for 119-BGA from 000000 to 101000

 

 

 

 

Added seperate row for 165 -FBGA Device Width (23:18)

 

 

 

 

Changed ΘJA and ΘJC for TQFP Package from 31 and 6 °C/W to 28.66 and 4.08 °C/W

 

 

 

 

respectively

 

 

 

 

Changed ΘJA and ΘJC for BGA Package from 45 and 7 °C/W to 23.8 and 6.2 °C/W

 

 

 

 

respectively

 

 

 

 

Changed ΘJA and ΘJC for FBGA Package from 46 and 3 °C/W to 20.7 and 4.0 °C/W

 

 

 

 

respectively

 

 

 

 

Modified VOL, VOH test conditions

 

 

 

 

Removed comment of ‘Pb-free BG packages availability’ below the Ordering Infor-

 

 

 

 

mation

 

 

 

 

Updated Ordering Information Table

*C

418125

See ECN

NXR

Converted from Preliminary to Final

 

 

 

 

Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901

 

 

 

 

North First Street” to “198 Champion Court”

 

 

 

 

Changed the description of IX from Input Load Current to Input Leakage Current on

 

 

 

 

page# 18

 

 

 

 

Changed the IX current values of MODE on page # 18 from –5 ∝A and 30 ∝A

 

 

 

 

to –30 ∝A and 5 ∝A

 

 

 

 

Changed the IX current values of ZZ on page # 18 from –30 ∝A and 5 ∝A

 

 

 

 

to –5 ∝A and 30 ∝A

 

 

 

 

Changed VIH < VDD to VIH < VDDon page # 18

 

 

 

 

Replaced Package Name column with Package Diagram in the Ordering

 

 

 

 

Information table

 

 

 

 

Updated Ordering Information Table

*D

475009

See ECN

VKN

Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND

 

 

 

 

Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching

 

 

 

 

Characteristics table.

 

 

 

 

Updated the Ordering Information table.

*E

793579

See ECN

VKN

Added Part numbers CY7C1380FV25 and CY7C1382FV25

 

 

 

 

Added footnote# 3 regarding Chip Enable

 

 

 

 

Updated Ordering Information table

Document #: 38-05546 Rev. *E

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Contents Selection Guide Features250 MHz 200 MHz 167 MHz Unit Cypress Semiconductor CorporationLogic Block Diagram CY7C1382DV25/CY7C1382FV25 3 1M x Logic Block Diagram CY7C1380DV25/CY7C1380FV25 3 512K xCY7C1382DV25 1M x Pin Configurations Pin Tqfp Pinout 3 Chip EnableCY7C1380DV25 512K X CY7C1380FV25 512K x Pin Configurations Ball BGA PinoutCY7C1380DV25 512K x Pin Configurations Ball Fbga Pinout 3 Chip EnablePin Definitions Power supply inputs to the core of the deviceName Description Byte write select inputs, active LOW. Qualified withSingle Read Accesses Power supply for the IO circuitrySingle Write Accesses Initiated by Adsp Functional OverviewLinear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Burst SequencesCE1 CE2 CE3 Adsp Adsc ADV Write CLK Operation Add. UsedFunction CY7C1382DV25/CY7C1382FV25 Truth Table for Read/Write 6Function CY7C1380DV25/CY7C1380FV25 Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Controller Block Diagram TAP Instruction Set Bypass RegisterTAP Timing TAP AC Switching CharacteristicsParameter Description Min Max Unit Clock Hold Times5V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Output Load Equivalent Identification Register DefinitionsBall BGA Boundary Scan Order 13 Identification CodesInstruction Code Description Bit # Ball IDA11 Operating Range Electrical CharacteristicsMaximum Ratings Thermal Resistance CapacitanceAC Test Loads and Waveforms PackageSetup Times Switching Characteristics250 MHz 200 MHz 167 MHz Parameter Description Min Output TimesRead Cycle Timing Switching WaveformsWrite Cycle Timing 25 CLZ Read/Write Cycle Timing 25, 27DON’T Care ZZ Mode Timing 29Ordering Information CY7C1382DV25-250BZXI Document # 38-05546 Rev. *E Pin Thin Plastic Quad Flat pack 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document Number Issue Orig. Description of Change DateDocument History

CY7C1382DV25, CY7C1380DV25, CY7C1382FV25, CY7C1380FV25 specifications

The Cypress CY7C1380FV25, CY7C1382FV25, CY7C1380DV25, and CY7C1382DV25 are high-performance static random access memory (SRAM) devices distinguished by their reliability and efficiency. These components are designed for applications requiring fast data storage and retrieval, making them ideal for embedded systems, communication devices, and various consumer electronics.

One of the main features of these SRAMs is their access time. The CY7C1380FV25 and CY7C1382FV25 models come with a super-fast access time of 25 nanoseconds, ensuring that data can be retrieved with minimal delay. This characteristic is crucial for high-speed applications, such as networking equipment and automotive systems, where rapid data processing is essential.

Both families of devices offer a competitive data width configuration, with CY7C1380 series providing 8 bits and CY7C1382 series providing 16 bits. This flexibility allows designers to choose the appropriate configuration based on their specific application requirements. Additionally, they support a wide voltage range for ease of integration into various systems.

The CY7C1380FV25 and CY7C1380DV25 devices feature low power consumption, which is vital for battery-operated devices. With their advanced CMOS technology, they exhibit reduced static power requirements, helping to prolong battery life and improve overall system efficiency. The IDD (supply current) ratings are particularly low, making them suitable for energy-sensitive applications.

A notable characteristic of the Cypress memory devices is their asynchronous read and write operations, providing simple interfacing in a variety of designs. They are designed to operate under a wide range of temperature conditions; thus, they are well-suited for industrial applications where temperature fluctuations might be a concern.

Furthermore, the CY7C1382FV25 and CY7C1382DV25 models include features like burst mode capability, enabling faster sequential access, which is beneficial for high-speed data processing tasks. This allows these SRAMs to deliver enhanced performance critical in applications like video processing and real-time data acquisition.

In summary, the Cypress CY7C1380FV25, CY7C1382FV25, CY7C1380DV25, and CY7C1382DV25 are distinguished by their fast access times, low power consumption, and flexible data widths. Their advanced technologies and characteristics make them a reliable choice for a diverse range of high-performance applications, ensuring that engineers can effectively address their design challenges while meeting the demands of modern electronics.
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