Cypress CY7C1382FV25 manual Functional Overview, Ground for the IO circuitry, Single Read Accesses

Page 7

 

 

 

 

CY7C1380DV25, CY7C1380FV25

 

 

 

 

CY7C1382DV25, CY7C1382FV25

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin Definitions (continued)

 

 

 

 

 

Name

 

IO

Description

 

 

 

VSSQ

IO Ground

Ground for the IO circuitry.

VDDQ

IO Power Supply

Power supply for the IO circuitry.

MODE

Input-

Selects burst order. When tied to GND selects linear burst sequence. When tied to

 

Static

VDD or left floating selects interleaved burst sequence. This is a strap pin and must

 

 

 

 

remain static during device operation. Mode pin has an internal pull up.

 

 

 

TDO

JTAG serial output

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the

 

Synchronous

JTAG feature is not used, this pin must be disconnected. This pin is not available on

 

 

 

 

TQFP packages.

 

 

 

TDI

JTAG serial input

Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG

 

Synchronous

feature is not used, this pin can be disconnected or connected to VDD. This pin is not

 

 

 

 

available on TQFP packages.

 

 

 

TMS

JTAG serial input

Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG

 

Synchronous

feature is not used, this pin can be disconnected or connected to VDD. This pin is not

 

 

 

 

available on TQFP packages.

 

 

 

TCK

JTAG-Clock

Clock input to the JTAG circuitry. If the JTAG feature is not used, this pin must be

 

 

 

 

connected to VSS. This pin is not available on TQFP packages.

NC

 

–

No Connects. Not internally connected to the die

 

 

 

 

NC/(36M,72M,

 

–

These pins are not connected. They will be used for expansion to the 36M, 72M,

144M, 288M,

 

 

 

144M, 288M, 576M and 1G densities.

576M, 1G)

 

 

 

 

 

 

 

 

 

Functional Overview

All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 2.6 ns (250-MHz device).

The CY7C1380DV25/CY7C1382DV25/CY7C1380FV25/ CY7C1382FV25 supports secondary cache in systems using either a linear or interleaved burst sequence. The interleaved burst order supports Pentium® and i486™ processors. The linear burst sequence is suited for processors that use a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the processor address strobe (ADSP) or the controller address strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access.

Byte write operations are qualified with the byte write enable (BWE) and byte write select (BWX) inputs. A global write enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self timed write circuitry.

Three synchronous chip selects (CE1, CE2, CE3) and an asynchronous output enable (OE) provide for easy bank selection and output tri-state control. ADSP is ignored if CE1 is HIGH.

Single Read Accesses

This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) CE1, CE2, CE3 are all asserted active, and (3) the write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs (A) is stored into the address advancement logic and the address register while being presented to the memory array. The corresponding data is allowed to propagate to the input of the output registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within 2.6 ns (250-MHz device) if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always tri-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single Read cycles are supported. Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will tri-state immediately.

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and

(2)CE1, CE2, CE3 are all asserted active. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. The write signals (GW, BWE, and BWX) and ADV inputs are ignored during this first cycle.

Document #: 38-05546 Rev. *E

Page 7 of 29

[+] Feedback

Page 6 Page 8
Image 7
Page 6 Page 8
Contents Cypress Semiconductor Corporation FeaturesSelection Guide 250 MHz 200 MHz 167 MHz UnitLogic Block Diagram CY7C1382DV25/CY7C1382FV25 3 1M x Logic Block Diagram CY7C1380DV25/CY7C1380FV25 3 512K xCY7C1380DV25 512K X Pin Configurations Pin Tqfp Pinout 3 Chip EnableCY7C1382DV25 1M x CY7C1380FV25 512K x Pin Configurations Ball BGA PinoutCY7C1380DV25 512K x Pin Configurations Ball Fbga Pinout 3 Chip EnableByte write select inputs, active LOW. Qualified with Power supply inputs to the core of the devicePin Definitions Name DescriptionFunctional Overview Power supply for the IO circuitrySingle Read Accesses Single Write Accesses Initiated by AdspBurst Sequences Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND ZZ Mode Electrical CharacteristicsCE1 CE2 CE3 Adsp Adsc ADV Write CLK Operation Add. UsedFunction CY7C1380DV25/CY7C1380FV25 Truth Table for Read/Write 6Function CY7C1382DV25/CY7C1382FV25 TAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set Bypass RegisterHold Times TAP AC Switching CharacteristicsTAP Timing Parameter Description Min Max Unit ClockIdentification Register Definitions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions 5V TAP AC Output Load EquivalentBit # Ball ID Identification CodesBall BGA Boundary Scan Order 13 Instruction Code DescriptionA11 Maximum Ratings Electrical CharacteristicsOperating Range Package CapacitanceThermal Resistance AC Test Loads and WaveformsOutput Times Switching CharacteristicsSetup Times 250 MHz 200 MHz 167 MHz Parameter Description MinRead Cycle Timing Switching WaveformsWrite Cycle Timing 25 CLZ Read/Write Cycle Timing 25, 27DON’T Care ZZ Mode Timing 29Ordering Information CY7C1382DV25-250BZXI Document # 38-05546 Rev. *E Pin Thin Plastic Quad Flat pack 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Orig. Description of Change DateDocument Number

CY7C1382DV25, CY7C1380DV25, CY7C1382FV25, CY7C1380FV25 specifications

The Cypress CY7C1380FV25, CY7C1382FV25, CY7C1380DV25, and CY7C1382DV25 are high-performance static random access memory (SRAM) devices distinguished by their reliability and efficiency. These components are designed for applications requiring fast data storage and retrieval, making them ideal for embedded systems, communication devices, and various consumer electronics.

One of the main features of these SRAMs is their access time. The CY7C1380FV25 and CY7C1382FV25 models come with a super-fast access time of 25 nanoseconds, ensuring that data can be retrieved with minimal delay. This characteristic is crucial for high-speed applications, such as networking equipment and automotive systems, where rapid data processing is essential.

Both families of devices offer a competitive data width configuration, with CY7C1380 series providing 8 bits and CY7C1382 series providing 16 bits. This flexibility allows designers to choose the appropriate configuration based on their specific application requirements. Additionally, they support a wide voltage range for ease of integration into various systems.

The CY7C1380FV25 and CY7C1380DV25 devices feature low power consumption, which is vital for battery-operated devices. With their advanced CMOS technology, they exhibit reduced static power requirements, helping to prolong battery life and improve overall system efficiency. The IDD (supply current) ratings are particularly low, making them suitable for energy-sensitive applications.

A notable characteristic of the Cypress memory devices is their asynchronous read and write operations, providing simple interfacing in a variety of designs. They are designed to operate under a wide range of temperature conditions; thus, they are well-suited for industrial applications where temperature fluctuations might be a concern.

Furthermore, the CY7C1382FV25 and CY7C1382DV25 models include features like burst mode capability, enabling faster sequential access, which is beneficial for high-speed data processing tasks. This allows these SRAMs to deliver enhanced performance critical in applications like video processing and real-time data acquisition.

In summary, the Cypress CY7C1380FV25, CY7C1382FV25, CY7C1380DV25, and CY7C1382DV25 are distinguished by their fast access times, low power consumption, and flexible data widths. Their advanced technologies and characteristics make them a reliable choice for a diverse range of high-performance applications, ensuring that engineers can effectively address their design challenges while meeting the demands of modern electronics.
Top Page Image Contents