Cypress CY7C1446AV33, CY7C1440AV33 Performing a TAP Reset, TAP Registers, TAP Instruction Set

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CY7C1440AV33

CY7C1442AV33

CY7C1446AV33

Performing a TAP Reset

A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating.

At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state.

TAP Registers

Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the Tap Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section.

When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path.

Bypass Register

To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed.

Boundary Scan Register

The boundary scan register is connected to all the input and bidirectional balls on the SRAM.

The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the I/O ring.

The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table.

TAP Instruction Set

Overview

Eight different instructions are possible with the three bit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are listed as RESERVED and should not be used. The other five instruc- tions are described in detail below.

Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state.

The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High-Z state until the next command is given during the “Update IR” state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the in- struction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is cap- tured in the boundary scan register.

The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possi- ble that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible.

To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register.

Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the bound- ary scan register between the TDI and TDO pins.

PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells pri-

or to the selection of another boundary scan test operation.

Document #: 38-05383 Rev. *E

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Contents Features Functional Description1Selection Guide 250 MHz 200 MHz 167 MHz UnitLogic Block Diagram CY7C1440AV33 1M x Logic Block Diagram CY7C1442AV33 2M xCY7C1440AV33 Pin Configurations Pin Tqfp Pinout CY7C1442AV33 2M xCY7C1442AV33 2M x Pin Definitions Name DescriptionByte Write Select Inputs, active LOW. Qualified with Power supply inputs to the core of the device Power supply for the I/O circuitryGround for the core of the device Ground for the I/O circuitryFunctional Overview Interleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Truth Table for Read/Write4,8,9 Truth Table for Read/Write4, 8Write Cycle, Suspend Burst Function CY7C1440AV33TAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag Performing a TAP Reset TAP RegistersTAP Instruction Set TAP Timing BypassTAP AC Switching Characteristics Over the operating Range10 3V TAP AC Test Conditions5V TAP AC Test Conditions 5V TAP AC Output Load EquivalentTAP DC Electrical Characteristics And Operating Conditions Identification Register DefinitionsScan Register Sizes Identification CodesBall Fbga Boundary Scan Order 14,15 SAMPLE/PRELOADBypass CY7C1440AV33 1M x 36, CY7C1442AV33 2M x Bit # Ball IDBall Fbga Boundary Scan Order 14 CY7C1446AV33 512K x Bit # Ball IDElectrical Characteristics Over the Operating Range17 Maximum RatingsOperating Range Ambient RangeCapacitance19 Thermal ResistanceAC Test Loads and Waveforms Switching Characteristics Over the Operating Range 24 250 200 167 Parameter Description Unit MinMin Max Set-up TimesSwitching Waveforms Read Cycle Timing26Write Cycle Timing26 Read/Write Cycle Timing26, 28 CLZZZ Mode Timing30 DON’T CareOrdering Information 250 Package Diagrams Pin Tqfp 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Issue Date Orig. Description of Change Document HistoryDocument Number AC Switching Characteristics table Updated the Ordering Information table473650 VKN
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