Cypress CY7C1440AV33, CY7C1446AV33 Capacitance19, Thermal Resistance, AC Test Loads and Waveforms

Page 19

CY7C1440AV33

CY7C1442AV33

CY7C1446AV33

Capacitance[19]

Parameter

Description

Test Conditions

100 TQFP

165 FBGA

209 FBGA

Unit

Max.

Max.

Max.

 

 

 

 

 

 

 

CIN

Input Capacitance

TA = 25°C, f = 1 MHz,

6.5

7

5

pF

 

 

VDD = 3.3V

 

 

 

 

CCLK

Clock Input Capacitance

3

7

5

pF

VDDQ = 2.5V

CI/O

Input/Output Capacitance

5.5

6

7

pF

 

Thermal Resistance[19]

 

 

 

 

 

Parameter

Description

Test Conditions

100 TQFP

165 FBGA

209 FBGA

Unit

Package

Package

Package

 

 

 

 

 

 

 

ΘJA

Thermal Resistance

Test conditions follow standard

25.21

20.8

25.31

°C/W

 

(Junction to Ambient)

test methods and procedures

 

 

 

 

 

 

for measuring thermal

 

 

 

 

ΘJC

Thermal Resistance

2.28

3.2

4.48

°C/W

impedance, per EIA/JESD51.

 

(Junction to Case)

 

 

 

 

 

AC Test Loads and Waveforms

3.3V I/O Test Load

 

 

 

 

 

 

 

 

 

 

R = 317

OUTPUT

 

 

 

 

 

 

 

 

 

 

3.3V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Z0

= 50

 

 

 

 

OUTPUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RL

= 50

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5 pF

 

 

 

 

 

 

 

 

 

 

 

 

 

R = 351

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INCLUDING

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VT = 1.5V

 

JIG AND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SCOPE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(a)

 

 

 

 

 

 

 

(b)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2.5V I/O Test Load

 

 

 

 

 

 

 

 

 

 

R = 1667

OUTPUT

 

 

 

 

 

 

 

 

 

 

2.5V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Z0

= 50

 

 

 

 

OUTPUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RL

= 50

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5 pF

 

 

 

 

 

 

 

 

 

 

 

 

 

R = 1538

 

 

 

 

 

 

 

 

 

 

 

INCLUDING

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VT = 1.25V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

JIG AND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(a)

 

SCOPE

 

 

 

 

 

 

(b)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note:

19. Tested initially and after any design or process change that may affect these parameters.

ALL INPUT PULSES

VDDQ

 

 

 

 

 

 

 

 

90%

 

 

10%

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(c)

 

 

 

 

 

 

 

 

 

 

 

VDDQ

 

 

 

 

ALL INPUT PULSES

 

 

 

 

 

 

 

 

90%

 

 

10%

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(c)

90%

10%

1ns

90%

10%

1ns

Document #: 38-05383 Rev. *E

Page 19 of 31

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Contents 250 MHz 200 MHz 167 MHz Unit FeaturesFunctional Description1 Selection GuideLogic Block Diagram CY7C1442AV33 2M x Logic Block Diagram CY7C1440AV33 1M xCY7C1440AV33 CY7C1442AV33 2M x Pin Configurations Pin Tqfp PinoutCY7C1442AV33 2M x Name Description Pin DefinitionsByte Write Select Inputs, active LOW. Qualified with Ground for the I/O circuitry Power supply inputs to the core of the devicePower supply for the I/O circuitry Ground for the core of the deviceFunctional Overview Linear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Function CY7C1440AV33 Truth Table for Read/Write4,8,9Truth Table for Read/Write4, 8 Write Cycle, Suspend BurstTAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Registers Performing a TAP ResetTAP Instruction Set Bypass TAP Timing5V TAP AC Output Load Equivalent TAP AC Switching Characteristics Over the operating Range103V TAP AC Test Conditions 5V TAP AC Test ConditionsIdentification Codes TAP DC Electrical Characteristics And Operating ConditionsIdentification Register Definitions Scan Register Sizes CY7C1440AV33 1M x 36, CY7C1442AV33 2M x Bit # Ball ID Ball Fbga Boundary Scan Order 14,15 SAMPLE/PRELOAD BypassCY7C1446AV33 512K x Bit # Ball ID Ball Fbga Boundary Scan Order 14Ambient Range Electrical Characteristics Over the Operating Range17Maximum Ratings Operating RangeThermal Resistance Capacitance19AC Test Loads and Waveforms Set-up Times Switching Characteristics Over the Operating Range 24250 200 167 Parameter Description Unit Min Min MaxRead Cycle Timing26 Switching WaveformsWrite Cycle Timing26 CLZ Read/Write Cycle Timing26, 28DON’T Care ZZ Mode Timing30Ordering Information 250 Pin Tqfp 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document History Issue Date Orig. Description of ChangeDocument Number VKN AC Switching Characteristics tableUpdated the Ordering Information table 473650