Cypress CY7C1440AV33, CY7C1446AV33, CY7C1442AV33 manual Write Cycle Timing26

Page 22

CY7C1440AV33

CY7C1442AV33

CY7C1446AV33

Switching Waveforms (continued)

Write Cycle Timing[26, 27]

 

 

tCYC

 

 

 

 

 

 

 

 

 

CLK

 

tCH

tCL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tADS

tADH

 

 

 

 

 

 

 

 

 

 

ADSP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tADS

tADH

 

 

 

ADSC extends burst

 

 

 

 

 

 

 

 

 

 

tADS

tADH

 

 

 

 

 

 

 

 

 

 

 

 

 

ADSC

 

 

 

 

 

 

 

 

 

 

 

 

 

tAS

tAH

 

 

 

 

 

 

 

 

 

 

ADDRESS

 

A1

 

 

A2

 

 

 

 

A3

 

 

 

 

Byte write signals are

 

 

 

 

 

 

 

 

 

 

ignored for first cycle when

 

 

 

 

 

 

tWES tWEH

 

 

 

ADSP initiates burst

 

 

 

 

 

 

 

BWE,

 

 

 

 

 

 

 

 

 

 

 

 

BWX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tWES tWEH

 

 

 

 

 

 

GW

 

 

 

 

 

 

 

 

 

 

 

 

 

tCES

tCEH

 

 

 

 

 

 

 

 

 

 

CE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tADVS tADVH

 

ADV

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADV suspends burst

 

 

 

 

OE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tDS

tDH

 

 

 

 

 

 

 

 

Data In (D)

High-Z

t

D(A1)

D(A2)

D(A2 + 1)

D(A2 + 1)

D(A2 + 2)

D(A2 + 3)

D(A3)

D(A3 + 1)

D(A3 + 2)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OEHZ

 

 

 

 

 

 

 

 

 

 

Data Out (Q)

 

 

 

 

 

 

 

 

 

 

 

 

BURST READ

Single WRITE

BURST WRITE

 

DON’T CARE

UNDEFINED

Note:

27. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.

Extended BURST WRITE

Document #: 38-05383 Rev. *E

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Contents Selection Guide FeaturesFunctional Description1 250 MHz 200 MHz 167 MHz UnitLogic Block Diagram CY7C1440AV33 1M x Logic Block Diagram CY7C1442AV33 2M xCY7C1440AV33 Pin Configurations Pin Tqfp Pinout CY7C1442AV33 2M xCY7C1442AV33 2M x Name Description Pin DefinitionsByte Write Select Inputs, active LOW. Qualified with Ground for the core of the device Power supply inputs to the core of the devicePower supply for the I/O circuitry Ground for the I/O circuitryFunctional Overview Linear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Write Cycle, Suspend Burst Truth Table for Read/Write4,8,9Truth Table for Read/Write4, 8 Function CY7C1440AV33TAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Registers Performing a TAP ResetTAP Instruction Set TAP Timing Bypass5V TAP AC Test Conditions TAP AC Switching Characteristics Over the operating Range103V TAP AC Test Conditions 5V TAP AC Output Load EquivalentScan Register Sizes TAP DC Electrical Characteristics And Operating ConditionsIdentification Register Definitions Identification CodesBypass Ball Fbga Boundary Scan Order 14,15SAMPLE/PRELOAD CY7C1440AV33 1M x 36, CY7C1442AV33 2M x Bit # Ball IDBall Fbga Boundary Scan Order 14 CY7C1446AV33 512K x Bit # Ball IDOperating Range Electrical Characteristics Over the Operating Range17Maximum Ratings Ambient RangeThermal Resistance Capacitance19AC Test Loads and Waveforms Min Max Switching Characteristics Over the Operating Range 24250 200 167 Parameter Description Unit Min Set-up TimesSwitching Waveforms Read Cycle Timing26Write Cycle Timing26 Read/Write Cycle Timing26, 28 CLZZZ Mode Timing30 DON’T CareOrdering Information 250 Package Diagrams Pin Tqfp 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document History Issue Date Orig. Description of ChangeDocument Number 473650 AC Switching Characteristics tableUpdated the Ordering Information table VKN