Cypress CY7C1440AV33 Ball Fbga Boundary Scan Order 14,15, Sample/Preload, Bypass, Bit # Ball ID

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CY7C1440AV33

CY7C1442AV33

CY7C1446AV33

Identification Codes (continued)

Instruction	Code	Description
SAMPLE/PRELOAD	100	Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
		Does not affect SRAM operation.
RESERVED	101	Do Not Use: This instruction is reserved for future use.

RESERVED	110	Do Not Use: This instruction is reserved for future use.

BYPASS	111	Places the bypass register between TDI and TDO. This operation does not affect SRAM
		operations.

165-ball FBGA Boundary Scan Order [14,15]

CY7C1440AV33 (1M x 36), CY7C1442AV33 (2M x 18)
Bit #	ball ID		Bit #	ball ID		Bit #	ball ID

1	N6		26	E11		51	A3
2	N7		27	D11		52	A2

3	N10		28	G10		53	B2

4	P11		29	F10		54	C2

5	P8		30	E10		55	B1

6	R8		31	D10		56	A1

7	R9		32	C11		57	C1

8	P9		33	A11		58	D1

9	P10		34	B11		59	E1

10	R10		35	A10		60	F1

11	R11		36	B10		61	G1

12	H11		37	A9		62	D2

13	N11		38	B9		63	E2

14	M11		39	C10		64	F2

15	L11		40	A8		65	G2

16	K11		41	B8		66	H1

17	J11		42	A7		67	H3

18	M10		43	B7		68	J1

19	L10		44	B6		69	K1

20	K10		45	A6		70	L1

21	J10		46	B5		71	M1

22	H9		47	A5		72	J2
23	H10		48	A4		73	K2

24	G11		49	B4		74	L2

25	F11		50	B3		75	M2

Bit #

ball ID

76N1

77N2

78P1

79R1

80R2

81P3

82R3

83P2

84R4

85P4

86N5

87P6

88R6

89Internal

Notes:

14.Balls that are NC (No Connect) are preset LOW.

15.Bit# 89 is preset HIGH.

Document #: 38-05383 Rev. *E

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Contents Features Functional Description1Selection Guide 250 MHz 200 MHz 167 MHz UnitLogic Block Diagram CY7C1440AV33 1M x Logic Block Diagram CY7C1442AV33 2M xCY7C1440AV33 Pin Configurations Pin Tqfp Pinout CY7C1442AV33 2M xCY7C1442AV33 2M x Name Description Pin DefinitionsByte Write Select Inputs, active LOW. Qualified with Power supply inputs to the core of the device Power supply for the I/O circuitryGround for the core of the device Ground for the I/O circuitryFunctional Overview Linear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Truth Table for Read/Write4,8,9 Truth Table for Read/Write4, 8Write Cycle, Suspend Burst Function CY7C1440AV33TAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Registers Performing a TAP ResetTAP Instruction Set TAP Timing BypassTAP AC Switching Characteristics Over the operating Range10 3V TAP AC Test Conditions5V TAP AC Test Conditions 5V TAP AC Output Load EquivalentTAP DC Electrical Characteristics And Operating Conditions Identification Register DefinitionsScan Register Sizes Identification CodesBall Fbga Boundary Scan Order 14,15 SAMPLE/PRELOADBypass CY7C1440AV33 1M x 36, CY7C1442AV33 2M x Bit # Ball IDBall Fbga Boundary Scan Order 14 CY7C1446AV33 512K x Bit # Ball IDElectrical Characteristics Over the Operating Range17 Maximum RatingsOperating Range Ambient RangeThermal Resistance Capacitance19AC Test Loads and Waveforms Switching Characteristics Over the Operating Range 24 250 200 167 Parameter Description Unit MinMin Max Set-up TimesSwitching Waveforms Read Cycle Timing26Write Cycle Timing26 Read/Write Cycle Timing26, 28 CLZZZ Mode Timing30 DON’T CareOrdering Information 250 Package Diagrams Pin Tqfp 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document History Issue Date Orig. Description of ChangeDocument Number AC Switching Characteristics table Updated the Ordering Information table473650 VKN