Cypress CY7C1440AV33, CY7C1446AV33, CY7C1442AV33 manual TAP Timing, Bypass

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CY7C1440AV33

CY7C1442AV33

CY7C1446AV33

The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required—that is, while data captured is shifted out, the preloaded data can be shifted in.

BYPASS

When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.

EXTEST

The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift-DR controller state.

EXTEST OUTPUT BUS TRI-STATE

IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode.

The boundary scan register has a special bit located at, bit #89 (for 165-FBGA package) or bit #138 (for 209-FBGA package). When this scan cell, called the “extest output bus tri-state”, is latched into the preload register during the “Update-DR” state in the TAP controller, it will directly control the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place the output bus into a High-Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the “Shift-DR” state. During “Update-DR”, the value loaded into that shift-register cell will latch into the preload register. When the EXTEST instruction is entered, this bit will directly control the output Q-bus pins. Note that this bit is pre-set HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the “Test-Logic-Reset” state.

Reserved

These instructions are not implemented but are reserved for future use. Do not use these instructions.

TAP Timing

12

Test Clock

(TCK)tTH

tTMSS tTMSH

Test Mode Select (TMS)

tTDIS tTDIH

Test Data-In (TDI)

3

4

5

6

tTL tCYC

tTDOV

tTDOX

Test Data-Out (TDO)

DON’T CARE

UNDEFINED

Document #: 38-05383 Rev. *E

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Contents Functional Description1 FeaturesSelection Guide 250 MHz 200 MHz 167 MHz UnitLogic Block Diagram CY7C1442AV33 2M x Logic Block Diagram CY7C1440AV33 1M xCY7C1440AV33 CY7C1442AV33 2M x Pin Configurations Pin Tqfp PinoutCY7C1442AV33 2M x Name Description Pin DefinitionsByte Write Select Inputs, active LOW. Qualified with Power supply for the I/O circuitry Power supply inputs to the core of the deviceGround for the core of the device Ground for the I/O circuitryFunctional Overview Linear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Truth Table for Read/Write4, 8 Truth Table for Read/Write4,8,9Write Cycle, Suspend Burst Function CY7C1440AV33TAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Registers Performing a TAP ResetTAP Instruction Set Bypass TAP Timing3V TAP AC Test Conditions TAP AC Switching Characteristics Over the operating Range105V TAP AC Test Conditions 5V TAP AC Output Load EquivalentIdentification Register Definitions TAP DC Electrical Characteristics And Operating ConditionsScan Register Sizes Identification CodesSAMPLE/PRELOAD Ball Fbga Boundary Scan Order 14,15Bypass CY7C1440AV33 1M x 36, CY7C1442AV33 2M x Bit # Ball IDCY7C1446AV33 512K x Bit # Ball ID Ball Fbga Boundary Scan Order 14Maximum Ratings Electrical Characteristics Over the Operating Range17Operating Range Ambient RangeThermal Resistance Capacitance19AC Test Loads and Waveforms 250 200 167 Parameter Description Unit Min Switching Characteristics Over the Operating Range 24Min Max Set-up TimesRead Cycle Timing26 Switching WaveformsWrite Cycle Timing26 CLZ Read/Write Cycle Timing26, 28DON’T Care ZZ Mode Timing30Ordering Information 250 Pin Tqfp 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document History Issue Date Orig. Description of ChangeDocument Number Updated the Ordering Information table AC Switching Characteristics table473650 VKN
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