Cypress CY7C1442AV33 manual Ball Fbga Boundary Scan Order 14, CY7C1446AV33 512K x Bit # Ball ID

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CY7C1440AV33

CY7C1442AV33

CY7C1446AV33

209-ball FBGA Boundary Scan Order [14, 16]

CY7C1446AV33 (512K x 72)
Bit #	ball ID		Bit #	ball ID		Bit #	ball ID		Bit #	ball ID

1	W6		36	F6		71	H6		106	K3

2	V6		37	K8		72	C6		107	K4
3	U6		38	K9		73	B6		108	K6

4	W7		39	K10		74	A6		109	K2

5	V7		40	J11		75	A5		110	L2

6	U7		41	J10		76	B5		111	L1

7	T7		42	H11		77	C5		112	M2

8	V8		43	H10		78	D5		113	M1

9	U8		44	G11		79	D4		114	N2

10	T8		45	G10		80	C4		115	N1

11	V9		46	F11		81	A4		116	P2

12	U9		47	F10		82	B4		117	P1

13	P6		48	E10		83	C3		118	R2

14	W11		49	E11		84	B3		119	R1

15	W10		50	D11		85	A3		120	T2

16	V11		51	D10		86	A2		121	T1

17	V10		52	C11		87	A1		122	U2

18	U11		53	C10		88	B2		123	U1

19	U10		54	B11		89	B1		124	V2

20	T11		55	B10		90	C2		125	V1

21	T10		56	A11		91	C1		126	W2

22	R11		57	A10		92	D2		127	W1

23	R10		58	C9		93	D1		128	T6

24	P11		59	B9		94	E1		129	U3

25	P10		60	A9		95	E2		130	V3

26	N11		61	D7		96	F2		131	T4

27	N10		62	C8		97	F1		132	T5

28	M11		63	B8		98	G1		133	U4

29	M10		64	A8		99	G2		134	V4

30	L11		65	D8		100	H2		135	5W

31	L10		66	C7		101	H1		136	5V

32	K11		67	B7		102	J2		137	5U

33	M6		68	A7		103	J1		138	Internal

34	L6		69	D6		104	K1

35	J6		70	G6		105	N6

Note:

16. Bit# 138 is preset HIGH.

Document #: 38-05383 Rev. *E

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Contents Functional Description1 FeaturesSelection Guide 250 MHz 200 MHz 167 MHz UnitLogic Block Diagram CY7C1442AV33 2M x Logic Block Diagram CY7C1440AV33 1M xCY7C1440AV33 CY7C1442AV33 2M x Pin Configurations Pin Tqfp PinoutCY7C1442AV33 2M x Byte Write Select Inputs, active LOW. Qualified with Pin DefinitionsName Description Power supply for the I/O circuitry Power supply inputs to the core of the deviceGround for the core of the device Ground for the I/O circuitryFunctional Overview ZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Truth Table for Read/Write4, 8 Truth Table for Read/Write4,8,9Write Cycle, Suspend Burst Function CY7C1440AV33Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Controller Block Diagram TAP Instruction Set Performing a TAP ResetTAP Registers Bypass TAP Timing 3V TAP AC Test Conditions TAP AC Switching Characteristics Over the operating Range10 5V TAP AC Test Conditions 5V TAP AC Output Load EquivalentIdentification Register Definitions TAP DC Electrical Characteristics And Operating ConditionsScan Register Sizes Identification CodesSAMPLE/PRELOAD Ball Fbga Boundary Scan Order 14,15Bypass CY7C1440AV33 1M x 36, CY7C1442AV33 2M x Bit # Ball IDCY7C1446AV33 512K x Bit # Ball ID Ball Fbga Boundary Scan Order 14Maximum Ratings Electrical Characteristics Over the Operating Range17Operating Range Ambient RangeAC Test Loads and Waveforms Capacitance19Thermal Resistance 250 200 167 Parameter Description Unit Min Switching Characteristics Over the Operating Range 24Min Max Set-up TimesRead Cycle Timing26 Switching WaveformsWrite Cycle Timing26 CLZ Read/Write Cycle Timing26, 28DON’T Care ZZ Mode Timing30Ordering Information 250 Pin Tqfp 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document Number Issue Date Orig. Description of ChangeDocument History Updated the Ordering Information table AC Switching Characteristics table473650 VKN