Cypress CY7C1442AV33, CY7C1446AV33, CY7C1440AV33 manual Ball Fbga 14 x 22 x 1.76 mm

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CY7C1440AV33

CY7C1442AV33

CY7C1446AV33

Package Diagrams (continued)

209-ball FBGA (14 x 22 x 1.76 mm) (51-85167)

51-85167-**

i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.

Document #: 38-05383 Rev. *E

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© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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Contents Functional Description1 FeaturesSelection Guide 250 MHz 200 MHz 167 MHz UnitLogic Block Diagram CY7C1442AV33 2M x Logic Block Diagram CY7C1440AV33 1M xCY7C1440AV33 CY7C1442AV33 2M x Pin Configurations Pin Tqfp PinoutCY7C1442AV33 2M x Byte Write Select Inputs, active LOW. Qualified with Pin DefinitionsName Description Power supply for the I/O circuitry Power supply inputs to the core of the deviceGround for the core of the device Ground for the I/O circuitryFunctional Overview ZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Truth Table for Read/Write4, 8 Truth Table for Read/Write4,8,9Write Cycle, Suspend Burst Function CY7C1440AV33Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Controller Block Diagram TAP Instruction Set Performing a TAP ResetTAP Registers Bypass TAP Timing3V TAP AC Test Conditions TAP AC Switching Characteristics Over the operating Range105V TAP AC Test Conditions 5V TAP AC Output Load EquivalentIdentification Register Definitions TAP DC Electrical Characteristics And Operating ConditionsScan Register Sizes Identification CodesSAMPLE/PRELOAD Ball Fbga Boundary Scan Order 14,15Bypass CY7C1440AV33 1M x 36, CY7C1442AV33 2M x Bit # Ball IDCY7C1446AV33 512K x Bit # Ball ID Ball Fbga Boundary Scan Order 14Maximum Ratings Electrical Characteristics Over the Operating Range17Operating Range Ambient RangeAC Test Loads and Waveforms Capacitance19Thermal Resistance 250 200 167 Parameter Description Unit Min Switching Characteristics Over the Operating Range 24Min Max Set-up TimesRead Cycle Timing26 Switching WaveformsWrite Cycle Timing26 CLZ Read/Write Cycle Timing26, 28DON’T Care ZZ Mode Timing30Ordering Information 250 Pin Tqfp 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document Number Issue Date Orig. Description of ChangeDocument History Updated the Ordering Information table AC Switching Characteristics table473650 VKN