Cypress CY7C1446AV33, CY7C1442AV33 manual CY7C1440AV33

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						CY7C1440AV33
						CY7C1442AV33
						CY7C1446AV33
Logic Block Diagram – CY7C1446AV33 (512K x 72)
A0, A1,A	ADDRESS
A0, A1,A	REGISTER
	REGISTER
		A[1:0]
MODE
ADV		BINARY	Q1
CLK		BINARY
		COUNTER
		CLR	Q0
ADSC
ADSP
BWH	DQH, DQPH		DQH, DQPH
BWH	WRITE DRIVER		WRITE DRIVER
BWG	DQF, DQPF		DQG, DQPG
BWG	WRITE DRIVER		WRITE DRIVER
BWF	DQF, DQPF		DQF, DQPF
BWF	WRITE DRIVER		WRITE DRIVER
BWE	DQE, DQPE		DQBYTE, DQP“a”E
BWE	WRITE DRIVER		WRITE DRIVER	MEMORY
				ARRAY
BWD	DQD, DQPD		DQD, DQPD
BWD	WRITE DRIVER		WRITE DRIVER
BWC	DQC, DQPC		DQC, DQPC
BWC	WRITE DRIVER		WRITE DRIVER		OUTPUT	OUTPUT
				SENSE		OUTPUT	DQs
						BUFFERS
					REGISTERS	BUFFERS
				AMPS	REGISTERS	E	DQPA
	DQB, DQPB		DQB, DQPB	AMPS			DQPA
			DQB, DQPB				DQPB
BWB			WRITE DRIVER				DQPB
BWB	WRITE DRIVER		WRITE DRIVER				DQPC
	WRITE DRIVER						DQPC
							DQPD
			DQA, DQPA				DQPE
	DQA, DQPA		DQA, DQPA				DQPF
BWA	DQA, DQPA		WRITE DRIVER				DQPF
	WRITE DRIVER		WRITE DRIVER				DQPG

BWE
BWE							DQPH
GW							INPUT
GW	ENABLE	PIPELINED					REGISTERS
CE1	REGISTER	PIPELINED
CE2	REGISTER	ENABLE
CE2		ENABLE
CE3
OE
ZZ	SLEEP
ZZ	CONTROL
	CONTROL

Document #: 38-05383 Rev. *E

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Contents 250 MHz 200 MHz 167 MHz Unit FeaturesFunctional Description1 Selection GuideLogic Block Diagram CY7C1442AV33 2M x Logic Block Diagram CY7C1440AV33 1M xCY7C1440AV33 CY7C1442AV33 2M x Pin Configurations Pin Tqfp PinoutCY7C1442AV33 2M x Pin Definitions Name DescriptionByte Write Select Inputs, active LOW. Qualified with Ground for the I/O circuitry Power supply inputs to the core of the devicePower supply for the I/O circuitry Ground for the core of the deviceFunctional Overview Interleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Function CY7C1440AV33 Truth Table for Read/Write4,8,9Truth Table for Read/Write4, 8 Write Cycle, Suspend BurstTAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag Performing a TAP Reset TAP RegistersTAP Instruction Set Bypass TAP Timing5V TAP AC Output Load Equivalent TAP AC Switching Characteristics Over the operating Range103V TAP AC Test Conditions 5V TAP AC Test ConditionsIdentification Codes TAP DC Electrical Characteristics And Operating ConditionsIdentification Register Definitions Scan Register SizesCY7C1440AV33 1M x 36, CY7C1442AV33 2M x Bit # Ball ID Ball Fbga Boundary Scan Order 14,15SAMPLE/PRELOAD BypassCY7C1446AV33 512K x Bit # Ball ID Ball Fbga Boundary Scan Order 14Ambient Range Electrical Characteristics Over the Operating Range17Maximum Ratings Operating RangeCapacitance19 Thermal ResistanceAC Test Loads and Waveforms Set-up Times Switching Characteristics Over the Operating Range 24250 200 167 Parameter Description Unit Min Min MaxRead Cycle Timing26 Switching WaveformsWrite Cycle Timing26 CLZ Read/Write Cycle Timing26, 28DON’T Care ZZ Mode Timing30Ordering Information 250 Pin Tqfp 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Issue Date Orig. Description of Change Document HistoryDocument Number VKN AC Switching Characteristics tableUpdated the Ordering Information table 473650

CY7C1440AV33

CY7C1446AV33

Logic Block Diagram – CY7C1446AV33 (512K x 72)

CLR

WRITE DRIVER