Cypress manual Logic Block Diagram CY7C1440AV33 1M x, Logic Block Diagram CY7C1442AV33 2M x

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								CY7C1440AV33
								CY7C1442AV33
								CY7C1446AV33
Logic Block Diagram – CY7C1440AV33 (1M x 36)
A0, A1, A	ADDRESS
	ADDRESS
	REGISTER		2	A[1:0]
			2	A[1:0]
MODE
ADV				Q1
CLK			BURST
		COUNTER
		CLR	AND	Q0
ADSC			LOGIC
ADSC
ADSP
	DQD ,DQPD			DQD ,DQPD
BWD	BYTE			BYTE
	WRITE REGISTER			WRITE DRIVER
	DQC ,DQPC			DQC ,DQPC
BWC	BYTE			BYTE				OUTPUT
	WRITE REGISTER			WRITE DRIVER	MEMORY	SENSE	OUTPUT	OUTPUT	DQs
	WRITE REGISTER			WRITE DRIVER	MEMORY		OUTPUT	BUFFERS
					ARRAY		REGISTERS	BUFFERS
				DQB ,DQPB	ARRAY	AMPS	REGISTERS	E	DQPA
	DQB ,DQPB					AMPS			DQPA
	DQB ,DQPB								DQPB
BWB	BYTE			BYTE					DQPB
				BYTE					DQPC
				WRITE DRIVER
	WRITE REGISTER			WRITE DRIVER
	WRITE REGISTER								DQPD
									DQPD
	DQA ,DQPA			DQA ,DQPA
	DQA ,DQPA			BYTE
BWA	BYTE			BYTE
BWA	BYTE			WRITE DRIVER
BWE	WRITE REGISTER			WRITE DRIVER
BWE	WRITE REGISTER
GW									INPUT
GW	ENABLE	PIPELINED							REGISTERS
CE1	REGISTER	PIPELINED
CE1		ENABLE
CE2


CE3
OE
ZZ	SLEEP
ZZ	CONTROL
	CONTROL
Logic Block Diagram – CY7C1442AV33 (2M x 18)

A0, A1, A

MODE

ADV

CLK

ADSC

ADSP

BWB

BWA

BWE

GW

CE1

CE2

CE3

OE

ADDRESS
REGISTER
	2	A[1:0]
	BURST	Q1
	COUNTER AND
	LOGIC
	CLR	Q0
DQB,DQPB
WRITE REGISTER
DQA,DQPA
WRITE REGISTER
ENABLE	PIPELINED
REGISTER	PIPELINED
	ENABLE

DQB,DQPB

WRITE DRIVER

DQA,DQPA

WRITE DRIVER

MEMORY

ARRAY

SENSE AMPS

OUTPUT

REGISTERS

OUTPUT BUFFERS

E

DQs

DQPA

DQPB

INPUT

REGISTERS

ZZ

SLEEP

CONTROL

Document #: 38-05383 Rev. *E

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Contents Selection Guide FeaturesFunctional Description1 250 MHz 200 MHz 167 MHz UnitLogic Block Diagram CY7C1440AV33 1M x Logic Block Diagram CY7C1442AV33 2M xCY7C1440AV33 Pin Configurations Pin Tqfp Pinout CY7C1442AV33 2M xCY7C1442AV33 2M x Byte Write Select Inputs, active LOW. Qualified with Pin DefinitionsName Description Ground for the core of the device Power supply inputs to the core of the devicePower supply for the I/O circuitry Ground for the I/O circuitryFunctional Overview ZZ Mode Electrical Characteristics Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Write Cycle, Suspend Burst Truth Table for Read/Write4,8,9Truth Table for Read/Write4, 8 Function CY7C1440AV33Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Controller Block Diagram TAP Instruction Set Performing a TAP ResetTAP Registers TAP Timing Bypass5V TAP AC Test Conditions TAP AC Switching Characteristics Over the operating Range103V TAP AC Test Conditions 5V TAP AC Output Load EquivalentScan Register Sizes TAP DC Electrical Characteristics And Operating ConditionsIdentification Register Definitions Identification CodesBypass Ball Fbga Boundary Scan Order 14,15SAMPLE/PRELOAD CY7C1440AV33 1M x 36, CY7C1442AV33 2M x Bit # Ball IDBall Fbga Boundary Scan Order 14 CY7C1446AV33 512K x Bit # Ball IDOperating Range Electrical Characteristics Over the Operating Range17Maximum Ratings Ambient RangeAC Test Loads and Waveforms Capacitance19Thermal Resistance Min Max Switching Characteristics Over the Operating Range 24250 200 167 Parameter Description Unit Min Set-up TimesSwitching Waveforms Read Cycle Timing26Write Cycle Timing26 Read/Write Cycle Timing26, 28 CLZZZ Mode Timing30 DON’T CareOrdering Information 250 Package Diagrams Pin Tqfp 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document Number Issue Date Orig. Description of ChangeDocument History 473650 AC Switching Characteristics tableUpdated the Ordering Information table VKN