Cypress CY7C1474V25, CY7C1470V25, CY7C1472V25 manual Ieee 1149.1 Serial Boundary Scan Jtag

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CY7C1470V25

CY7C1472V25

CY7C1474V25

IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C1470V25/CY7C1472V25/CY7C1474V25 incorpo- rates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC-standard 2.5V or 1.8V I/O logic levels.

The CY7C1470V25/CY7C1472V25/CY7C1474V25 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register.

Disabling the JTAG Feature

Test MODE SELECT (TMS)

The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block Diagram.)

It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are inter- nally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device.

Test Data-Out (TDO)

The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See Tap Controller State Diagram.)

TAP Controller Block Diagram

TAP Controller State Diagram

1

TEST-LOGIC

 

 

 

 

 

RESET

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

0

RUN-TEST/

1

SELECT

1

SELECT

1

IDLE

 

DR-SCAN

 

IR-SCAN

 

 

 

 

 

 

 

 

0

 

0

 

 

 

 

1

 

1

 

 

 

 

CAPTURE-DR

 

CAPTURE-IR

 

 

 

 

0

 

0

 

 

 

 

SHIFT-DR

0

SHIFT-IR

0

 

 

 

1

 

1

 

 

 

 

EXIT1-DR

1

EXIT1-IR

1

 

 

 

 

 

TDI

Selection Circuitry

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bypass Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Instruction Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31

30

29

.

.

.

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Identification Register

 

 

 

 

 

 

 

 

 

 

x

.

.

.

.

.

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Boundary Scan Register

Selection Circuitry

TDO

 

0

 

 

0

 

PAUSE-DR

0

PAUSE-IR

0

 

1

 

 

1

 

0

 

 

0

 

 

EXIT2-DR

 

EXIT2-IR

 

 

1

 

 

1

 

UPDATE-DR

 

UPDATE-IR

 

1

0

 

1

0

 

TCK

TMS

 

TAP CONTROLLER

 

Performing a TAP Reset

A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating.

The 0/1 next to each state represents the value of TMS at the rising edge of TCK.

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.

At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state.

TAP Registers

Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK.

Document #: 38-05290 Rev. *I

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Contents Functional Description FeaturesLogic Block Diagram-CY7C1470V25 2M x Cypress Semiconductor CorporationSelection Guide Logic Block Diagram-CY7C1472V25 4M xLogic Block Diagram-CY7C1474V25 1M x 250 MHz 200 MHz 167 MHz UnitPin Configurations Pin Tqfp Pinout 4M ×CY7C1472V25 4M x Pin Name Type Pin Description Pin DefinitionsByte Write Select Inputs, active L OW . Qualified with Power supply for the I/O circuitry Power supply inputs to the core of the deviceClock input to the Jtag circuitry Single Write Accesses Single Read AccessesBurst Read Accesses Burst Write AccessesInterleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Function CY7C1472V25 Partial Write Cycle Description1, 2, 3Function CY7C1470V25 BW d BW c BW b BW a Function CY7C1474V25TAP Controller Block Diagram TAP Controller State Diagram Ieee 1149.1 Serial Boundary Scan JtagInstruction Register TAP Instruction SetParameter Description Min Max Unit Clock TAP AC Switching Characteristics Over the Operating Range9TAP Timing Output Times8V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions Identification Register DefinitionsRegister Name Bit Size Scan Register SizesIdentification Codes Instruction Code DescriptionBoundary Scan Exit Order 4M x Boundary Scan Exit Order 2M xBit # Ball ID J10 Boundary Scan Exit Order 1M xA11 W10Operating Range Electrical Characteristics Over the Operating Range12Maximum Ratings Ambient RangeThermal Resistance14 Capacitance14AC Test Loads and Waveforms 250 200 167 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range 15Set-up Times Address A1 A2 Switching WaveformsRead/Write/Timing21, 22 DON’T CareZZ Mode Timing25 NOP, Stall and Deselect Cycles21, 22Ordering Information 250 Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm ECN No Issue Date Orig. Description of Change Document History472335 See ECN VKN

CY7C1474V25, CY7C1470V25, CY7C1472V25 specifications

The Cypress CY7C1470V25, CY7C1474V25, and CY7C1472V25 are part of Cypress Semiconductor’s family of high-performance synchronous static random-access memory (SRAM) solutions. These memory devices are designed specifically for applications that require fast access times and high bandwidth, making them ideal for a variety of consumer and industrial applications.

One of the standout features of these SRAMs is their performance. They provide high-speed access times, with data transfer rates that can reach up to 1 GHz. This performance is particularly beneficial for high-speed applications including networking equipment, telecommunications, and video processing systems. The CY7C1470V25, for example, offers a 256K x 16 configuration with an access time as low as 3.5 ns. Similarly, the CY7C1474V25 and CY7C1472V25 variants provide respective memory sizes of 1M x 16 and 512K x 16, catering to diverse memory application needs.

These SRAMs utilize a synchronous interface, which provides greater control over data transfers and synchronization with external clock signals. This synchronous operation allows for more efficient data handling in high-speed environments, reducing latency and improving system performance overall.

In terms of power consumption, the Cypress CY7C147x series is designed to operate efficiently. With a low operating voltage of 2.5V, these devices minimize energy usage while still delivering high-speed performance. The low standby power makes them suitable for battery-operated devices, as well as for systems where energy efficiency is a priority.

Furthermore, these SRAMs come with built-in features such as burst mode, which allows for sequential data access, enhancing read and write operations. This is especially useful in applications requiring rapid data retrieval.

The packaging options for the CY7C1470V25, CY7C1474V25, and CY7C1472V25 include both fine-pitch ball grid array (FBGA) and other configurations, facilitating easy integration into various circuit board layouts.

In conclusion, the Cypress CY7C1470V25, CY7C1474V25, and CY7C1472V25 SRAMs are powerful memory solutions that combine high-speed performance, low power consumption, and a synchronous interface. Their robust design makes them suitable for a wide array of applications ranging from communications to consumer electronics, ensuring they meet the demands of modern technology.
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