Cypress CY7C1470V25 manual TAP Timing, TAP AC Switching Characteristics Over the Operating Range9

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CY7C1470V25

CY7C1472V25

CY7C1474V25

possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register.

Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO balls.

Note that since the PRELOAD part of the command is not implemented, putting the TAP to the Update-DR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command.

BYPASS

When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.

Reserved

These instructions are not implemented but are reserved for future use. Do not use these instructions.

TAP Timing

12

Test Clock

(TCK)tTH

tTMSS tTMSH

Test Mode Select (TMS)

tTDIS tTDIH

Test Data-In (TDI)

3

4

5

6

tTL tCYC

tTDOV

tTDOX

Test Data-Out

 

(TDO)

 

DON’T CARE

UNDEFINED

TAP AC Switching Characteristics Over the Operating Range[9, 10]

Parameter

Description

Min.

Max.

Unit

Clock

 

 

 

 

tTCYC

TCK Clock Cycle Time

50

 

ns

tTF

TCK Clock Frequency

 

20

MHz

tTH

TCK Clock HIGH time

20

 

ns

tTL

TCK Clock LOW time

20

 

ns

Output Times

 

 

 

 

 

 

 

 

tTDOV

TCK Clock LOW to TDO Valid

 

10

ns

tTDOX

TCK Clock LOW to TDO Invalid

0

 

ns

Set-up Times

 

 

 

 

 

 

 

 

 

tTMSS

TMS Set-up to TCK Clock Rise

5

 

ns

tTDIS

TDI Set-up to TCK Clock Rise

5

 

ns

tCS

Capture Set-up to TCK Rise

5

 

ns

Hold Times

 

 

 

 

tTMSH

TMS Hold after TCK Clock Rise

5

 

ns

tTDIH

TDI Hold after Clock Rise

5

 

ns

tCH

Capture Hold after Clock Rise

5

 

ns

Notes:

9.tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.

10. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.

Document #: 38-05290 Rev. *I

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Contents Features Logic Block Diagram-CY7C1470V25 2M xFunctional Description Cypress Semiconductor CorporationLogic Block Diagram-CY7C1472V25 4M x Logic Block Diagram-CY7C1474V25 1M xSelection Guide 250 MHz 200 MHz 167 MHz UnitPin Configurations Pin Tqfp Pinout 4M ×CY7C1472V25 4M x Pin Definitions Pin Name Type Pin DescriptionByte Write Select Inputs, active L OW . Qualified with Power supply inputs to the core of the device Power supply for the I/O circuitryClock input to the Jtag circuitry Single Read Accesses Burst Read AccessesSingle Write Accesses Burst Write AccessesLinear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Partial Write Cycle Description1, 2, 3 Function CY7C1470V25 BW d BW c BW b BW aFunction CY7C1472V25 Function CY7C1474V25TAP Controller Block Diagram TAP Controller State Diagram Ieee 1149.1 Serial Boundary Scan JtagInstruction Register TAP Instruction SetTAP AC Switching Characteristics Over the Operating Range9 TAP TimingParameter Description Min Max Unit Clock Output TimesTAP DC Electrical Characteristics And Operating Conditions 5V TAP AC Test Conditions8V TAP AC Test Conditions Identification Register DefinitionsScan Register Sizes Identification CodesRegister Name Bit Size Instruction Code DescriptionBoundary Scan Exit Order 2M x Boundary Scan Exit Order 4M xBit # Ball ID Boundary Scan Exit Order 1M x A11J10 W10Electrical Characteristics Over the Operating Range12 Maximum RatingsOperating Range Ambient RangeCapacitance14 Thermal Resistance14AC Test Loads and Waveforms Switching Characteristics Over the Operating Range 15 250 200 167 Parameter Description Unit Min MaxSet-up Times Switching Waveforms Read/Write/Timing21, 22Address A1 A2 DON’T CareZZ Mode Timing25 NOP, Stall and Deselect Cycles21, 22Ordering Information 250 Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm ECN No Issue Date Orig. Description of Change Document History472335 See ECN VKN

CY7C1474V25, CY7C1470V25, CY7C1472V25 specifications

The Cypress CY7C1470V25, CY7C1474V25, and CY7C1472V25 are part of Cypress Semiconductor’s family of high-performance synchronous static random-access memory (SRAM) solutions. These memory devices are designed specifically for applications that require fast access times and high bandwidth, making them ideal for a variety of consumer and industrial applications.

One of the standout features of these SRAMs is their performance. They provide high-speed access times, with data transfer rates that can reach up to 1 GHz. This performance is particularly beneficial for high-speed applications including networking equipment, telecommunications, and video processing systems. The CY7C1470V25, for example, offers a 256K x 16 configuration with an access time as low as 3.5 ns. Similarly, the CY7C1474V25 and CY7C1472V25 variants provide respective memory sizes of 1M x 16 and 512K x 16, catering to diverse memory application needs.

These SRAMs utilize a synchronous interface, which provides greater control over data transfers and synchronization with external clock signals. This synchronous operation allows for more efficient data handling in high-speed environments, reducing latency and improving system performance overall.

In terms of power consumption, the Cypress CY7C147x series is designed to operate efficiently. With a low operating voltage of 2.5V, these devices minimize energy usage while still delivering high-speed performance. The low standby power makes them suitable for battery-operated devices, as well as for systems where energy efficiency is a priority.

Furthermore, these SRAMs come with built-in features such as burst mode, which allows for sequential data access, enhancing read and write operations. This is especially useful in applications requiring rapid data retrieval.

The packaging options for the CY7C1470V25, CY7C1474V25, and CY7C1472V25 include both fine-pitch ball grid array (FBGA) and other configurations, facilitating easy integration into various circuit board layouts.

In conclusion, the Cypress CY7C1470V25, CY7C1474V25, and CY7C1472V25 SRAMs are powerful memory solutions that combine high-speed performance, low power consumption, and a synchronous interface. Their robust design makes them suitable for a wide array of applications ranging from communications to consumer electronics, ensuring they meet the demands of modern technology.
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