Cypress CY7C1474V25, CY7C1470V25 Functional Overview, Single Read Accesses, Burst Read Accesses

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CY7C1470V25

CY7C1472V25

CY7C1474V25

Functional Overview

The CY7C1470V25/CY7C1472V25/CY7C1474V25 are synchronous-pipelined Burst NoBL SRAMs designed specifi- cally to eliminate wait states during Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 3.0 ns (250-MHz device).

Accesses can be initiated by asserting all three Chip Enables (CE1, CE2, CE3) active at the rising edge of the clock. If Clock Enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a Read or Write operation, depending on the status of the Write Enable (WE). BW[x] can be used to conduct Byte Write operations.

Write operations are qualified by the Write Enable (WE). All writes are simplified with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) simplify depth expansion. All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD should be driven LOW once the device has been deselected in order to load a new address for the next operation.

Single Read Accesses

ARead access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, (3) the Write Enable input signal WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory core and control logic. The control logic determines that a Read access is in progress and allows the requested data to propagate to the input of the output register. At the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 2.6 ns (250-MHz device) provided OE is active LOW. After the first clock of the Read access the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. During the second clock, a subsequent operation (Read/Write/Deselect) can be initiated. Deselecting the device is also pipelined. Therefore, when the SRAM is deselected at clock rise by one of the chip enable signals, its output will tri-state following the next clock rise.

Burst Read Accesses

The CY7C1470V25/CY7C1472V25/CY7C1474V25 have an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap-around when incre- mented sufficiently. A HIGH input on ADV/LD will increment

Document #: 38-05290 Rev. *I

the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence.

Single Write Accesses

Write accesses are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, and (3) the Write signal WE is asserted LOW. The address presented to the address inputs is loaded into the Address Register. The Write signals are latched into the Control Logic block.

On the subsequent clock rise the data lines are automatically tri-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQ and DQP

(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for CY7C1474V25, DQa,b,c,d/DQPa,b,c,d for CY7C1470V25 and DQa,b/DQPa,b for CY7C1472V25). In addition, the address for the subsequent access (Read/Write/Deselect) is latched into the Address Register (provided the appropriate control signals are asserted).

On the next clock rise the data presented to DQ and DQP

(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for CY7C1474V25, DQa,b,c,d/DQPa,b,c,d for CY7C1470V25 & DQa,b/DQPa,b for CY7C1472V25) (or a subset for Byte Write operations, see Write Cycle Description table for details) inputs is latched into the device and the Write is complete.

The data written during the Write operation is controlled by BW (BWa,b,c,d,e,f,g,h for CY7C1474V25, BWa,b,c,d for CY7C1470V25 and BWa,b for CY7C1472V25) signals. The CY7C1470V25/CY7C1472V25/CY7C1474V25 provides Byte Write capability that is described in the Write Cycle Description table. Asserting the Write Enable input (WE) with the selected Byte Write Select (BW) input will selectively write to only the desired bytes. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the Write operations. Byte Write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple Byte Write operations.

Because the CY7C1470V25/CY7C1472V25/CY7C1474V25 are common I/O devices, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQ and DQP (DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for CY7C1474V25, DQa,b,c,d/DQPa,b,c,d for CY7C1470V25 and DQa,b/DQPa,b for CY7C1472V25) inputs. Doing so will tri-state the output drivers. As a safety precaution, DQ and DQP

(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for CY7C1474V25, DQa,b,c,d/DQPa,b,c,d for CY7C1470V25 and DQa,b/DQPa,b for CY7C1472V25) are automatically tri-stated during the data portion of a Write cycle, regardless of the state of OE.

Burst Write Accesses

The CY7C1470V25/CY7C1472V25/CY7C1474V25 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above. When ADV/LD is driven HIGH on the subsequent clock rise, the Chip Enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BW (BWa,b,c,d,e,f,g,h for

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Contents Cypress Semiconductor Corporation FeaturesLogic Block Diagram-CY7C1470V25 2M x Functional Description250 MHz 200 MHz 167 MHz Unit Logic Block Diagram-CY7C1472V25 4M xLogic Block Diagram-CY7C1474V25 1M x Selection Guide4M × Pin Configurations Pin Tqfp PinoutCY7C1472V25 4M x Pin Name Type Pin Description Pin DefinitionsByte Write Select Inputs, active L OW . Qualified with Power supply for the I/O circuitry Power supply inputs to the core of the deviceClock input to the Jtag circuitry Burst Write Accesses Single Read AccessesBurst Read Accesses Single Write AccessesInterleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Function CY7C1474V25 Partial Write Cycle Description1, 2, 3Function CY7C1470V25 BW d BW c BW b BW a Function CY7C1472V25Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller Block Diagram TAP Controller State DiagramTAP Instruction Set Instruction RegisterOutput Times TAP AC Switching Characteristics Over the Operating Range9TAP Timing Parameter Description Min Max Unit ClockIdentification Register Definitions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions 8V TAP AC Test ConditionsInstruction Code Description Scan Register SizesIdentification Codes Register Name Bit SizeBoundary Scan Exit Order 4M x Boundary Scan Exit Order 2M xBit # Ball ID W10 Boundary Scan Exit Order 1M xA11 J10Ambient Range Electrical Characteristics Over the Operating Range12Maximum Ratings Operating RangeThermal Resistance14 Capacitance14AC Test Loads and Waveforms 250 200 167 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range 15Set-up Times DON’T Care Switching WaveformsRead/Write/Timing21, 22 Address A1 A2NOP, Stall and Deselect Cycles21, 22 ZZ Mode Timing25Ordering Information 250 Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document History ECN No Issue Date Orig. Description of ChangeVKN 472335 See ECN

CY7C1474V25, CY7C1470V25, CY7C1472V25 specifications

The Cypress CY7C1470V25, CY7C1474V25, and CY7C1472V25 are part of Cypress Semiconductor’s family of high-performance synchronous static random-access memory (SRAM) solutions. These memory devices are designed specifically for applications that require fast access times and high bandwidth, making them ideal for a variety of consumer and industrial applications.

One of the standout features of these SRAMs is their performance. They provide high-speed access times, with data transfer rates that can reach up to 1 GHz. This performance is particularly beneficial for high-speed applications including networking equipment, telecommunications, and video processing systems. The CY7C1470V25, for example, offers a 256K x 16 configuration with an access time as low as 3.5 ns. Similarly, the CY7C1474V25 and CY7C1472V25 variants provide respective memory sizes of 1M x 16 and 512K x 16, catering to diverse memory application needs.

These SRAMs utilize a synchronous interface, which provides greater control over data transfers and synchronization with external clock signals. This synchronous operation allows for more efficient data handling in high-speed environments, reducing latency and improving system performance overall.

In terms of power consumption, the Cypress CY7C147x series is designed to operate efficiently. With a low operating voltage of 2.5V, these devices minimize energy usage while still delivering high-speed performance. The low standby power makes them suitable for battery-operated devices, as well as for systems where energy efficiency is a priority.

Furthermore, these SRAMs come with built-in features such as burst mode, which allows for sequential data access, enhancing read and write operations. This is especially useful in applications requiring rapid data retrieval.

The packaging options for the CY7C1470V25, CY7C1474V25, and CY7C1472V25 include both fine-pitch ball grid array (FBGA) and other configurations, facilitating easy integration into various circuit board layouts.

In conclusion, the Cypress CY7C1470V25, CY7C1474V25, and CY7C1472V25 SRAMs are powerful memory solutions that combine high-speed performance, low power consumption, and a synchronous interface. Their robust design makes them suitable for a wide array of applications ranging from communications to consumer electronics, ensuring they meet the demands of modern technology.
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