Cypress CY7C1470V25, CY7C1474V25 Document History, ECN No Issue Date Orig. Description of Change

Page 27

CY7C1470V25

CY7C1472V25

CY7C1474V25

Document History Page

Document Title: CY7C1470V25/CY7C1472V25/CY7C1474V25 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture

Document Number: 38-05290

REV.

ECN No.

Issue Date

Orig. of

Description of Change

Change

 

 

 

 

 

**

114677

08/06/02

PKS

New data sheet

 

 

 

 

 

*A

121519

01/27/03

CJM

Updated features for package offering

 

 

 

 

Removed 300-MHz offering

 

 

 

 

Changed tCO, tEOV, tCHZ, tEOHZ from 2.4 ns to 2.6 ns (250 MHz), tDOH, tCLZ

 

 

 

 

from 0.8 ns to 1.0 ns (250 MHz), tDOH, tCLZ from 1.0 ns to 1.3 ns (200 MHz)

 

 

 

 

Updated ordering information

 

 

 

 

Changed Advanced Information to Preliminary

*B

223721

See ECN

NJY

Changed timing diagrams

 

 

 

 

Changed logic block diagrams

 

 

 

 

Modified Functional Description

 

 

 

 

Modified “Functional Overview” section

 

 

 

 

Added boundary scan order for all packages

 

 

 

 

Included thermal numbers and capacitance values for all packages

 

 

 

 

Included IDD and ISB values

 

 

 

 

Removed 250-MHz offering and included 225-MHz speed bin

 

 

 

 

Changed package outline for 165FBGA package and 209-ball BGA package

 

 

 

 

Removed 119-BGA package offering

*C

235012

See ECN

RYQ

Minor Change: The data sheets do not match on the spec system and

 

 

 

 

external web

*D

243572

See ECN

NJY

Changed ball C11,D11,E11,F11,G11 from DQPb,DQb,DQb,DQb,DQb to

 

 

 

 

DQPa,DQa,DQa,DQa,DQa in page 4

 

 

 

 

Modified capacitance values in page 19

*E

299511

See ECN

SYT

Removed 225-MHz offering and included 250-MHz speed bin

 

 

 

 

Changed tCYC from 4.4 ns to 4.0 ns for 250-MHz Speed Bin

 

 

 

 

Changed ΘJA from 16.8 to 24.63 °C/W and ΘJC from 3.3 to 2.28 °C/W for 100

 

 

 

 

TQFP Package on Page # 19

 

 

 

 

Added lead-free information for 100-Pin TQFP and 165 FBGA Packages

 

 

 

 

Added comment of ‘Lead-free BG packages availability’ below the Ordering

 

 

 

 

Information

*F

320197

See ECN

PCI

Corrected typo in part numbers on page# 9 and 10

 

 

 

 

 

*G

331513

See ECN

PCI

Address expansion pins/balls in the pinouts for all packages are modified as per

 

 

 

 

JEDEC standard

 

 

 

 

Added Address Expansion pins in the Pin Definitions Table

 

 

 

 

Added Industrial Operating Range

 

 

 

 

Modified VOL, VOH Test Conditions

 

 

 

 

Updated Ordering Information Table

*H

416221

See ECN

RXU

Converted from Preliminary to Final

 

 

 

 

Changed address of Cypress Semiconductor Corporation on Page# 1 from

 

 

 

 

“3901 North First Street” to “198 Champion Court”

 

 

 

 

Changed Three-state to Tri-state

 

 

 

 

Changed the description of IX from Input Load Current to Input Leakage Current

 

 

 

 

on page# 17

 

 

 

 

Changed the IX current values of MODE on page # 17 from –5 ∝A and 30 ∝A

 

 

 

 

to –30 ∝A and 5 ∝A

 

 

 

 

Changed the IX current values of ZZ on page # 17 from –30 ∝A and 5 ∝A

 

 

 

 

to –5 ∝A and 30 ∝A

 

 

 

 

Changed VDDQ < VDD to VDDQ < VDD on page #17

 

 

 

 

Replaced Package Name column with Package Diagram in the Ordering Infor-

 

 

 

 

mation table

 

 

 

 

Updated Ordering Information table

Document #: 38-05290 Rev. *I

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Contents Cypress Semiconductor Corporation FeaturesLogic Block Diagram-CY7C1470V25 2M x Functional Description250 MHz 200 MHz 167 MHz Unit Logic Block Diagram-CY7C1472V25 4M xLogic Block Diagram-CY7C1474V25 1M x Selection Guide4M × Pin Configurations Pin Tqfp PinoutCY7C1472V25 4M x Pin Definitions Pin Name Type Pin DescriptionByte Write Select Inputs, active L OW . Qualified with Power supply inputs to the core of the device Power supply for the I/O circuitryClock input to the Jtag circuitry Burst Write Accesses Single Read AccessesBurst Read Accesses Single Write AccessesLinear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Function CY7C1474V25 Partial Write Cycle Description1, 2, 3Function CY7C1470V25 BW d BW c BW b BW a Function CY7C1472V25Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller Block Diagram TAP Controller State DiagramTAP Instruction Set Instruction RegisterOutput Times TAP AC Switching Characteristics Over the Operating Range9TAP Timing Parameter Description Min Max Unit ClockIdentification Register Definitions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions 8V TAP AC Test ConditionsInstruction Code Description Scan Register SizesIdentification Codes Register Name Bit SizeBoundary Scan Exit Order 2M x Boundary Scan Exit Order 4M xBit # Ball ID W10 Boundary Scan Exit Order 1M xA11 J10Ambient Range Electrical Characteristics Over the Operating Range12Maximum Ratings Operating RangeCapacitance14 Thermal Resistance14AC Test Loads and Waveforms Switching Characteristics Over the Operating Range 15 250 200 167 Parameter Description Unit Min MaxSet-up Times DON’T Care Switching WaveformsRead/Write/Timing21, 22 Address A1 A2NOP, Stall and Deselect Cycles21, 22 ZZ Mode Timing25Ordering Information 250 Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x 1.76 mm Document History ECN No Issue Date Orig. Description of ChangeVKN 472335 See ECN

CY7C1474V25, CY7C1470V25, CY7C1472V25 specifications

The Cypress CY7C1470V25, CY7C1474V25, and CY7C1472V25 are part of Cypress Semiconductor’s family of high-performance synchronous static random-access memory (SRAM) solutions. These memory devices are designed specifically for applications that require fast access times and high bandwidth, making them ideal for a variety of consumer and industrial applications.

One of the standout features of these SRAMs is their performance. They provide high-speed access times, with data transfer rates that can reach up to 1 GHz. This performance is particularly beneficial for high-speed applications including networking equipment, telecommunications, and video processing systems. The CY7C1470V25, for example, offers a 256K x 16 configuration with an access time as low as 3.5 ns. Similarly, the CY7C1474V25 and CY7C1472V25 variants provide respective memory sizes of 1M x 16 and 512K x 16, catering to diverse memory application needs.

These SRAMs utilize a synchronous interface, which provides greater control over data transfers and synchronization with external clock signals. This synchronous operation allows for more efficient data handling in high-speed environments, reducing latency and improving system performance overall.

In terms of power consumption, the Cypress CY7C147x series is designed to operate efficiently. With a low operating voltage of 2.5V, these devices minimize energy usage while still delivering high-speed performance. The low standby power makes them suitable for battery-operated devices, as well as for systems where energy efficiency is a priority.

Furthermore, these SRAMs come with built-in features such as burst mode, which allows for sequential data access, enhancing read and write operations. This is especially useful in applications requiring rapid data retrieval.

The packaging options for the CY7C1470V25, CY7C1474V25, and CY7C1472V25 include both fine-pitch ball grid array (FBGA) and other configurations, facilitating easy integration into various circuit board layouts.

In conclusion, the Cypress CY7C1470V25, CY7C1474V25, and CY7C1472V25 SRAMs are powerful memory solutions that combine high-speed performance, low power consumption, and a synchronous interface. Their robust design makes them suitable for a wide array of applications ranging from communications to consumer electronics, ensuring they meet the demands of modern technology.
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