Cypress CY7C1545V18, CY7C1543V18, CY7C1556V18 manual Capacitance, AC Electrical Characteristics

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CY7C1541V18, CY7C1556V18

CY7C1543V18, CY7C1545V18

Electrical Characteristics (continued)

DC Electrical Characteristics

Over the Operating Range [15]

Parameter	Description	Test Conditions			Min	Typ	Max	Unit
ISB1	Automatic Power down	Max VDD,	375 MHz	x8			525	mA
	Current	Both Ports Deselected,
	Current	Both Ports Deselected,		x9			525
		VIN ≥ VIH or VIN ≤ VIL		x9			525
		VIN ≥ VIH or VIN ≤ VIL
		f = fMAX = 1/tCYC, Inputs		x18			525
		Static
		Static		x36			410
				x36			410

			333 MHz	x8			500	mA

				x9			500

				x18			500

				x36			395

			300 MHz	x8			450	mA

				x9			450

				x18			450

				x36			385

AC Electrical Characteristics

Over the Operating Range[14]

Parameter	Description	Test Conditions	Min	Typ	Max	Unit
VIH	Input HIGH Voltage		VREF + 0.2	–	VDDQ + 0.24	V
VIL	Input LOW Voltage		–0.24	–	VREF – 0.2	V

Capacitance

Tested initially and after any design or process change that may affect these parameters.

Parameter	Description	Test Conditions	Max	Unit
CIN	Input Capacitance	TA = 25°C, f = 1 MHz, VDD = 1.8V, VDDQ = 1.5V	5	pF
CCLK	Clock Input Capacitance		6	pF
CO	Output Capacitance		7	pF

Document Number: 001-05389 Rev. *F

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Contents Configurations FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1541V18 Logic Block Diagram CY7C1556V18Doff Logic Block Diagram CY7C1545V18 Logic Block Diagram CY7C1543V18Ball Fbga 15 x 17 x 1.4 mm Pinout Pin ConfigurationCY7C1541V18 8M x CY7C1556V18 8M xCY7C1543V18 4M x WPS BWSCY7C1545V18 4M x Pin Definitions Pin Name Pin DescriptionNegative Input Clock Input Power Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceTDO for Jtag TCK Pin for JtagRead Operations Functional OverviewWrite Operations Byte Write OperationsApplication Example Valid Data Indicator QvldDepth Expansion Programmable ImpedanceWrite Cycle Descriptions Truth TableOperation CommentsWrite cycle description table for CY7C1545V18 follows Write cycle description table for CY7C1556V18 followsDevice Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Sample Z State diagram for the TAP controller follows.12 TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsRegister Name Bit Size Instruction Code DescriptionBit # Bump ID Power Up Sequence in QDR-II+ Sram Power Up SequenceDLL Constraints DC Electrical Characteristics Electrical CharacteristicsMaximum Ratings Operating RangeAC Electrical Characteristics CapacitanceParameter Description Test Conditions Max Unit Thermal Resistance Parameter Description Test Conditions Fbga UnitThermal Resistance Junction to Case Consortium Description 375 MHz 333 MHz 300 MHz Unit Switching CharacteristicsParameter Min Max HighRead/Write/Deselect Sequence 31, 32 Switching WaveformsOrdering Information 300 Ball Fbga 15 x 17 x 1.4 mm Package DiagramIGS VEENXR VKN/FSU