Cypress CY7C1543V18 manual Pin Configuration, Ball Fbga 15 x 17 x 1.4 mm Pinout, CY7C1541V18 8M x

Page 4

CY7C1541V18, CY7C1556V18

CY7C1543V18, CY7C1545V18

Pin Configuration

The pin configuration for CY7C1541V18, CY7C1556V18, CY7C1543V18, and CY7C1545V18 follow.[2]

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1541V18 (8M x 8)

1

2

3

4

5

6

7

8

9

10

11

A

A

A

1

NC/144M

A

A

CQ

CQ

WPS

NWS

K

RPS

B

NC

NC

NC

A

NC/288M

K

0

A

NC

NC

Q3

NWS

C

NC

NC

NC

VSS

A

NC

A

VSS

NC

NC

D3

D

NC

D4

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

NC

E

NC

NC

Q4

VDDQ

VSS

VSS

VSS

VDDQ

NC

D2

Q2

F

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

G

NC

D5

Q5

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

Q1

D1

K

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

L

NC

Q6

D6

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

Q0

M

NC

NC

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

D0

N

NC

D7

NC

VSS

A

A

A

VSS

NC

NC

NC

P

NC

NC

Q7

A

A

QVLD

A

A

NC

NC

NC

R

TDO

TCK

A

A

A

NC

A

A

A

TMS

TDI

CY7C1556V18 (8M x 9)

1

2

3

4

5

6

7

8

9

10

11

A

A

A

NC

NC/144M

A

A

CQ

CQ

WPS

K

RPS

B

NC

NC

NC

A

NC/288M

K

0

A

NC

NC

Q4

BWS

C

NC

NC

NC

VSS

A

NC

A

VSS

NC

NC

D4

D

NC

D5

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

NC

E

NC

NC

Q5

VDDQ

VSS

VSS

VSS

VDDQ

NC

D3

Q3

F

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

G

NC

D6

Q6

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

Q2

D2

K

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

L

NC

Q7

D7

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

Q1

M

NC

NC

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

D1

N

NC

D8

NC

VSS

A

A

A

VSS

NC

NC

NC

P

NC

NC

Q8

A

A

QVLD

A

A

NC

D0

Q0

R

TDO

TCK

A

A

A

NC

A

A

A

TMS

TDI

Note

2. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.

Document Number: 001-05389 Rev. *F

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Contents Features ConfigurationsFunctional Description Selection GuideLogic Block Diagram CY7C1556V18 Logic Block Diagram CY7C1541V18Doff Logic Block Diagram CY7C1543V18 Logic Block Diagram CY7C1545V18Pin Configuration Ball Fbga 15 x 17 x 1.4 mm PinoutCY7C1541V18 8M x CY7C1556V18 8M xWPS BWS CY7C1543V18 4M xCY7C1545V18 4M x Pin Name Pin Description Pin DefinitionsNegative Input Clock Input Power Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview Read OperationsWrite Operations Byte Write OperationsValid Data Indicator Qvld Application ExampleDepth Expansion Programmable ImpedanceTruth Table Write Cycle DescriptionsOperation CommentsWrite cycle description table for CY7C1556V18 follows Write cycle description table for CY7C1545V18 followsDevice Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Sample Z TAP Controller State Diagram State diagram for the TAP controller follows.12TAP Controller Block Diagram TAP Electrical CharacteristicsTAP AC Switching Characteristics TAP Timing and Test ConditionsIdentification Register Definitions Scan Register SizesRegister Name Bit Size Instruction Code DescriptionBit # Bump ID Power Up Sequence Power Up Sequence in QDR-II+ SramDLL Constraints Electrical Characteristics DC Electrical CharacteristicsMaximum Ratings Operating RangeCapacitance AC Electrical CharacteristicsParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga Unit Thermal ResistanceThermal Resistance Junction to Case Switching Characteristics Consortium Description 375 MHz 333 MHz 300 MHz UnitParameter Min Max HighSwitching Waveforms Read/Write/Deselect Sequence 31, 32Ordering Information 300 Package Diagram Ball Fbga 15 x 17 x 1.4 mmVEE IGSNXR VKN/FSU