Cypress CY7C1543V18 Logic Block Diagram CY7C1541V18, Logic Block Diagram CY7C1556V18, Doff

CY7C1541V18, CY7C1556V18

CY7C1543V18, CY7C1545V18

Logic Block Diagram (CY7C1541V18)

8

D[7:0]

21Address

A(20:0) Register

K

K CLK

Gen.

DOFF

VREF
		Control
WPS
		Logic
NWS
	[1:0]

	Write	Write	Write	Write
	Reg	Reg	Reg	Reg
Decode	2M x	2M x	2M x	2M x	Decode
Write Add.	8 Array	8 Array	8 Array	8 Array	Read Add.
	Read Data Reg.
		32	16			Reg.
			16
							Reg.

Address	21	A(20:0)
Register

RPS

Control

Logic

				CQ
	8		CQ
Reg.
	8	8
	8		Q[7:0]
	8
			QVLD

Logic Block Diagram (CY7C1556V18)

9

D[8:0]

21Address

A(20:0) Register

K

K CLK

Gen.

DOFF

VREF
		Control
WPS
		Logic
BWS
	[0]

	Write	Write	Write	Write
	Reg	Reg	Reg	Reg
Decode	2M x	2M x	2M x	2M x	Decode
Write Add.	9 Array	9 Array	9 Array	9 Array	Read Add.
	Read Data Reg.
		36	18			Reg.
			18
							Reg.

Address	21	A(20:0)
Register

RPS

Control

Logic

				CQ
			CQ
	9
Reg.
	9	9
	9		Q[8:0]
	9
			QVLD

Document Number: 001-05389 Rev. *F Page 2 of 28

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