Cypress CY7C1541V18 manual TDO for Jtag, TCK Pin for Jtag, TDI Pin for Jtag, TMS Pin for Jtag

Page 7

 

 

 

 

 

 

CY7C1541V18, CY7C1556V18

 

 

 

 

 

 

CY7C1543V18, CY7C1545V18

 

 

 

 

 

 

Pin Definitions (continued)

 

 

 

 

 

 

 

Pin Name

IO

 

 

Pin Description

 

ZQ

Input

Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus

 

 

 

 

impedance. CQ, CQ and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected

 

 

 

 

between ZQ and ground. Alternately, this pin can be connected directly to VDDQ, which enables the

 

 

 

 

minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.

 

 

 

Input

DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device.The timings

 

DOFF

 

 

 

 

in the DLL turned off operation are different from those listed in this data sheet. For normal operation, this

 

 

 

 

pin can be connected to a pull up through a 10 KΩ or less pull up resistor. The device behaves in QDR-I

 

 

 

 

mode when the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167

 

 

 

 

MHz with QDR-I timing.

 

TDO

Output

TDO for JTAG.

 

 

 

 

 

TCK

Input

TCK Pin for JTAG.

 

 

 

 

 

TDI

Input

TDI Pin for JTAG.

 

 

 

 

 

TMS

Input

TMS Pin for JTAG.

 

 

 

 

 

NC

N/A

Not Connected to the Die. Can be tied to any voltage level.

 

 

 

 

 

NC/144M

N/A

Not Connected to the Die. Can be tied to any voltage level.

 

 

 

 

 

NC/288M

N/A

Not Connected to the Die. Can be tied to any voltage level.

 

 

 

 

 

VREF

Input-

Reference Voltage Input. Static input used to set the reference level for HSTL inputs and Outputs as

 

 

 

Reference

well as AC measurement points.

 

VDD

Power Supply

Power Supply Inputs to the Core of the Device.

 

VSS

Ground

Ground for the Device.

 

VDDQ

Power Supply

Power Supply Inputs for the Outputs of the Device.

Document Number: 001-05389 Rev. *F

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Contents Selection Guide FeaturesConfigurations Functional DescriptionLogic Block Diagram CY7C1556V18 Logic Block Diagram CY7C1541V18Doff Logic Block Diagram CY7C1545V18 Logic Block Diagram CY7C1543V18CY7C1556V18 8M x Pin ConfigurationBall Fbga 15 x 17 x 1.4 mm Pinout CY7C1541V18 8M xWPS BWS CY7C1543V18 4M xCY7C1545V18 4M x Pin Name Pin Description Pin DefinitionsNegative Input Clock Input TCK Pin for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagByte Write Operations Functional OverviewRead Operations Write OperationsProgrammable Impedance Valid Data Indicator QvldApplication Example Depth ExpansionComments Truth TableWrite Cycle Descriptions OperationInto the device. D359 remains unaltered Write cycle description table for CY7C1556V18 followsWrite cycle description table for CY7C1545V18 follows DeviceIeee 1149.1 Serial Boundary Scan Jtag Sample Z State diagram for the TAP controller follows.12 TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsInstruction Code Description Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBit # Bump ID Power Up Sequence Power Up Sequence in QDR-II+ SramDLL Constraints Operating Range Electrical CharacteristicsDC Electrical Characteristics Maximum RatingsCapacitance AC Electrical CharacteristicsParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga Unit Thermal ResistanceThermal Resistance Junction to Case High Switching CharacteristicsConsortium Description 375 MHz 333 MHz 300 MHz Unit Parameter Min MaxRead/Write/Deselect Sequence 31, 32 Switching WaveformsOrdering Information 300 Ball Fbga 15 x 17 x 1.4 mm Package DiagramVKN/FSU VEEIGS NXR
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