Cypress CY7C1545V18, CY7C1543V18, CY7C1556V18, CY7C1541V18 manual Ordering Information

Page 25

CY7C1541V18, CY7C1556V18

CY7C1543V18, CY7C1545V18

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered.

Speed	Ordering Code	Package	Package Type	Operating
(MHz)	Ordering Code	Diagram	Package Type	Range
375	CY7C1541V18-375BZC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Commercial

	CY7C1556V18-375BZC

	CY7C1543V18-375BZC

	CY7C1545V18-375BZC

	CY7C1541V18-375BZXC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1556V18-375BZXC

	CY7C1543V18-375BZXC

	CY7C1545V18-375BZXC

	CY7C1541V18-375BZI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Industrial

	CY7C1556V18-375BZI

	CY7C1543V18-375BZI

	CY7C1545V18-375BZI

	CY7C1541V18-375BZXI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1556V18-375BZXI

	CY7C1543V18-375BZXI

	CY7C1545V18-375BZXI

333	CY7C1541V18-333BZC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Commercial

	CY7C1556V18-333BZC

	CY7C1543V18-333BZC

	CY7C1545V18-333BZC

	CY7C1541V18-333BZXC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1556V18-333BZXC

	CY7C1543V18-333BZXC

	CY7C1545V18-333BZXC

	CY7C1541V18-333BZI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Industrial

	CY7C1556V18-333BZI

	CY7C1543V18-333BZI

	CY7C1545V18-333BZI

	CY7C1541V18-333BZXI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1556V18-333BZXI

	CY7C1543V18-333BZXI

	CY7C1545V18-333BZXI

Document Number: 001-05389 Rev. *F

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Contents Configurations FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1556V18 Logic Block Diagram CY7C1541V18Doff Logic Block Diagram CY7C1545V18 Logic Block Diagram CY7C1543V18Ball Fbga 15 x 17 x 1.4 mm Pinout Pin ConfigurationCY7C1541V18 8M x CY7C1556V18 8M xWPS BWS CY7C1543V18 4M xCY7C1545V18 4M x Pin Name Pin Description Pin DefinitionsNegative Input Clock Input Power Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceTDO for Jtag TCK Pin for JtagRead Operations Functional OverviewWrite Operations Byte Write OperationsApplication Example Valid Data Indicator QvldDepth Expansion Programmable ImpedanceWrite Cycle Descriptions Truth TableOperation CommentsWrite cycle description table for CY7C1545V18 follows Write cycle description table for CY7C1556V18 followsDevice Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Sample Z State diagram for the TAP controller follows.12 TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsRegister Name Bit Size Instruction Code DescriptionBit # Bump ID Power Up Sequence Power Up Sequence in QDR-II+ SramDLL Constraints DC Electrical Characteristics Electrical CharacteristicsMaximum Ratings Operating RangeCapacitance AC Electrical CharacteristicsParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga Unit Thermal ResistanceThermal Resistance Junction to Case Consortium Description 375 MHz 333 MHz 300 MHz Unit Switching CharacteristicsParameter Min Max HighRead/Write/Deselect Sequence 31, 32 Switching WaveformsOrdering Information 300 Ball Fbga 15 x 17 x 1.4 mm Package DiagramIGS VEENXR VKN/FSU