Cypress CY7C1545V18, CY7C1543V18 manual Identification Register Definitions, Scan Register Sizes

Page 17

CY7C1541V18, CY7C1556V18

CY7C1543V18, CY7C1545V18

Identification Register Definitions

	Instruction Field		Value			Description
	Instruction Field	CY7C1541V18	CY7C1556V18	CY7C1543V18	CY7C1545V18	Description
		CY7C1541V18	CY7C1556V18	CY7C1543V18	CY7C1545V18
	Revision Number	000	000	000	000	Version number.
	(31:29)
	Cypress Device ID	11010010101000100	11010010101001100	11010010101010100	11010010101100100	Defines the type of
	(28:12)					SRAM.
	Cypress JEDEC ID	00000110100	00000110100	00000110100	00000110100	Allows unique
	(11:1)					identification of
						SRAM vendor.
	ID Register	1	1	1	1	Indicates the
	Presence (0)					presence of an ID
						register.

Scan Register Sizes

Register Name	Bit Size
Instruction	3

Bypass	1

ID	32

Boundary Scan	109

Instruction Codes

Instruction	Code	Description
EXTEST	000	Captures the input and output ring contents.
IDCODE	001	Loads the ID register with the vendor ID code and places the register between TDI and TDO.
		This operation does not affect SRAM operation.
SAMPLE Z	010	Captures the input and output contents. Places the boundary scan register between TDI and
		TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED	011	Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD	100	Captures the input and output ring contents. Places the boundary scan register between TDI
		and TDO. Does not affect the SRAM operation.
RESERVED	101	Do Not Use: This instruction is reserved for future use.
RESERVED	110	Do Not Use: This instruction is reserved for future use.
BYPASS	111	Places the bypass register between TDI and TDO. This operation does not affect SRAM
		operation.

Document Number: 001-05389 Rev. *F

Page 17 of 28

[+] Feedback

Image 17

Contents Configurations FeaturesFunctional Description Selection GuideDoff Logic Block Diagram CY7C1541V18Logic Block Diagram CY7C1556V18 Logic Block Diagram CY7C1545V18 Logic Block Diagram CY7C1543V18Ball Fbga 15 x 17 x 1.4 mm Pinout Pin ConfigurationCY7C1541V18 8M x CY7C1556V18 8M xCY7C1545V18 4M x CY7C1543V18 4M xWPS BWS Negative Input Clock Input Pin DefinitionsPin Name Pin Description Power Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceTDO for Jtag TCK Pin for JtagRead Operations Functional OverviewWrite Operations Byte Write OperationsApplication Example Valid Data Indicator QvldDepth Expansion Programmable ImpedanceWrite Cycle Descriptions Truth TableOperation CommentsWrite cycle description table for CY7C1545V18 follows Write cycle description table for CY7C1556V18 followsDevice Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Sample Z State diagram for the TAP controller follows.12 TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsRegister Name Bit Size Instruction Code DescriptionBit # Bump ID DLL Constraints Power Up Sequence in QDR-II+ SramPower Up Sequence DC Electrical Characteristics Electrical CharacteristicsMaximum Ratings Operating RangeParameter Description Test Conditions Max Unit AC Electrical CharacteristicsCapacitance Thermal Resistance Junction to Case Thermal ResistanceParameter Description Test Conditions Fbga Unit Consortium Description 375 MHz 333 MHz 300 MHz Unit Switching CharacteristicsParameter Min Max HighRead/Write/Deselect Sequence 31, 32 Switching WaveformsOrdering Information 300 Ball Fbga 15 x 17 x 1.4 mm Package DiagramIGS VEENXR VKN/FSU