Cypress CY7C68014A, CY7C68013, CY7C68015A, CY7C68016A manual 128

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CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Figure 6. Signal

Port

GPIF Master

Slave FIFO

PD7

FD[15]

FD[15]

PD6

FD[14]

FD[14]

PD5

FD[13]

FD[13]

PD4

FD[12]

FD[12]

PD3

FD[11]

FD[11]

PD2

FD[10]

FD[10]

PD1

FD[9]

FD[9]

PD0

FD[8]

FD[8]

PB7

FD[7]

FD[7]

PB6

FD[6]

FD[6]

XTALIN

PB5

FD[5]

FD[5]

PB4

FD[4]

FD[4]

XTALOUT

PB3

FD[3]

FD[3]

RESET#

PB2

FD[2]

FD[2]

WAKEUP#

PB1

FD[1]

FD[1]

SCL

56

PB0

FD[0]

FD[0]

SDA

RDY0

SLRD

**PE0 replaces IFCLK

RDY1

SLWR

& PE1 replaces CLKOUT

CTL0

FLAGA

on CY7C68015A/16A

CTL1

FLAGB

**PE0

CTL2

FLAGC

**PE1

INT0#/PA0

INT0#/PA0

INT0#/ PA0

IFCLK

INT1#/PA1

INT1#/PA1

INT1#/ PA1

CLKOUT

PA2

PA2

SLOE

WU2/PA3

WU2/PA3

WU2/PA3

DPLUS

PA4

PA4

FIFOADR0

DMINUS

PA5

PA5

FIFOADR1

PA6

PA6

PKTEND

PA7

PA7

PA7/FLAGD/SLCS#

CTL3

CTL4

CTL5

RDY2

RDY3

100

RDY4

RDY5

BKPT

PORTC7/GPIFADR7

PORTC6/GPIFADR6

PORTC5/GPIFADR5

PORTC4/GPIFADR4

RxD0

PORTC3/GPIFADR3

TxD0

PORTC2/GPIFADR2

RxD1

PORTC1/GPIFADR1

TxD1

PORTC0/GPIFADR0

INT4

PE7/GPIFADR8

INT5#

T2

PE6/T2EX

T1

PE5/INT6

PE4/RxD1OUT

T0

PE3/RxD0OUT

PE2/T2OUT

RD#

PE1/T1OUT

PE0/T0OUT

WR#

D7

CS#

D6

OE#

D5

PSEN#

D4

D3

A15

D2

A14

D1

A13

D0

A12

A11

128

A10

A9

A8

A7

A6

A5

EA

A4

A3

A2

A1

A0

Document #: 38-08032 Rev. *L

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Contents Cypress Semiconductor Corporation 198 Champion Court Features CY7C68013A/14A/15A/16ALogic Block Diagram Features CY7C68013A/14A onlyFeatures CY7C68015A/16A only Functional Overview ApplicationsInterrupt System USB Boot MethodsBus-powered Applications ReNumerationINT2 USB Interrupts Priority INT2VEC Value SourceFIFO/GPIF Interrupt INT4 Reset Pin Reset and WakeupProgram/Data RAM Reset Timing Values ConditionInternal Code Memory, EA = Inside FX2LP Outside FX2LPExternal Code Memory, EA = Register AddressesSize × 64 bytes Endpoints 0 × 512 bytes Setup Data BufferEndpoint Configurations High -speed Mode Endpoint RAMArchitecture 12.5 Default Full-Speed Alternate SettingsMaster/Slave Control Signals External Fifo InterfaceUSB Uploads and Downloads Autopointer AccessECC Generation7 GpifPackage Description 18 I2C ControllerCompatible with Previous Generation EZ-USB FX2 Part Number Conversion TablePE1 Pin Assignments20 CY7C68013A/14A and CY7C68015A/16A Differences Ifclk PE0128 Pin Tqfp CY7C68013A/CY7C68014ACY7C68013A/CY7C68014A CY7C68013A/CY7C68014A 56-pin Ssop Pin Assignment CY7C68013A/CY7C68014A 56-pin SsopCY7C68015A/CY7C68016A Pin QFN CY7C68013A 56-pin Vfbga Pin Assignment Top View CY7C68013A/15A Pin Descriptions FX2LP Pin Descriptions 128 100 56 VF Name Type Default56 VF Name Type Default Description FX2LP Pin DescriptionsPort FIFOADR1 IFCONFIG1..0WU2 FIFOADR0PORTCCFG.1 GPIFADR0PORTCCFG.0 GPIFADR1T2OUT Port ET0OUT T1OUTGPIFADR8 RXD1OUTINT6 T2EXCTL4 FlagbFlagc CTL3Ground FX2LP Register Summary Register SummaryRegister can only be reset, it cannot be set Epie EP0CS E6CB Flowstb DPL0 = both read/write bit ΘJc + θCa Thermal CharacteristicsAbsolute Maximum Ratings Operating ConditionsDC Characteristics AC Electrical CharacteristicsUSB Transceiver Program Memory Read ClkoutProgram Memory Read Parameters Description Min Typ Max Unit Data Memory Read CLKOUT17Data Memory Read Parameters Description Min Typ Max Unit Data Memory Write Stretch =Data Memory Write Parameters Description Min Max Unit WR# Strobe Function when Portc is Accessed by Portc Strobe Feature TimingsGpif Synchronous Signals Timing Diagram20 Gpif Synchronous SignalsSlave Fifo Synchronous Read Slave Fifo Synchronous Read Timing Diagram20Slave Fifo Asynchronous Read Slave Fifo Asynchronous Read Timing Diagram20Slave Fifo Synchronous Write Slave Fifo Synchronous Write Timing Diagram20Slave Fifo Synchronous Packet End Strobe Slave Fifo Asynchronous WriteSlave Fifo Asynchronous Packet End Strobe Slave Fifo Synchronous Write Sequence and Timing DiagramSlave Fifo Address to Flags/Data Slave Fifo Output EnableRD/WR/PKTEND to FIFOADR10 Hold Time FIFOADR10 to SLRD/SLWR/PKTEND Setup TimeSlave Fifo Synchronous Address Slave Fifo Asynchronous AddressSingle and Burst Synchronous Read Example Sequence Diagram10.17.2 Single and Burst Synchronous Write Slave Fifo Asynchronous Read Sequence and Timing Diagram20 Sequence Diagram of a Single and Burst Asynchronous ReadSlave Fifo Asynchronous Write Sequence and Timing Diagram20 Sequence Diagram of a Single and Burst Asynchronous WriteDevelopment Tool Kit Ideal for battery powered applicationsIdeal for non-battery powered applications Ordering InformationLead Shrunk Small Outline Package O56 Package DiagramsLead QFN 8 x 8 mm LF56A Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A100RA Lead Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A128 Vfbga 5 x 5 x 1.0 mm 0.50 Pitch, 0.30 Ball BZ56 PCB Layout RecommendationsCross-section of the Area Underneath the QFN Package Quad Flat Package No Leads QFN Package Design NotesIssue Orig. Description of Change Date Pyrs Cmcc

CY7C68016A, CY7C68014A, CY7C68015A, CY7C68013 specifications

The Cypress CY7C68013, CY7C68015A, CY7C68014A, and CY7C68016A are part of Cypress Semiconductor's EZ-USB family of microcontrollers, known for their high performance and flexibility in USB applications. These devices are primarily used for USB interfacing and have gained popularity in various industries due to their robust features and capabilities.

One of the main features of the CY7C68013 is its Dual FIFO architecture, allowing for efficient data transfer between USB and the system memory. This feature optimizes throughput and reduces CPU overhead, making it an excellent choice for applications that require high-speed data exchange, such as video streaming, data acquisition, and industrial automation. The device is equipped with a USB 2.0 interface which supports full-speed operation at 12 Mbps, ensuring compatibility with a wide range of USB devices.

The CY7C68015A, a similar variant, offers additional memory options, providing users with the flexibility to select the necessary capacity for their specific applications. This part is particularly useful in scenarios that demand more users or higher data storage, making it ideal for complex USB peripherals like printers and multifunction devices. Moreover, it includes a unique capability of upgradeable firmware, ensuring that the device remains relevant and functional as technology evolves.

In contrast, the CY7C68014A stands out with its support for isochronous data transfers, making it suitable for real-time applications that require timely data delivery. This is particularly important in audio and video applications where delays can impact performance. The device incorporates advanced power management features, allowing it to operate efficiently both in low and high-power modes.

Lastly, the CY7C68016A integrates enhanced security features, positioning it as an ideal choice for applications that require data integrity and protection against unauthorized access. It supports various encryption standards and provides secure boot capabilities, making it suitable for secure environments such as financial transactions and sensitive data processing.

In summary, the CY7C68013, CY7C68015A, CY7C68014A, and CY7C68016A microcontrollers offer a versatile suite of features that cater to a wide array of USB applications. Their design emphasizes performance, flexibility, and security, making them essential components in today's rapidly evolving technology landscape. Whether in consumer electronics, industrial automation, or specialized applications, these devices provide the reliability and efficiency that engineers and developers require.