Cypress CY7C68013, CY7C68015A, CY7C68016A, CY7C68014A manual EP0CS

Page 32

CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Table 12. FX2LP Register Summary (continued)

Hex

Size

Name

Description

b7

b6

b5

b4

b3

b2

b1

b0

Default

Access

E69D

1

EP8BCL[11]

Endpoint 8 Byte Count L

BC7/SKIP

BC6

BC5

BC4

BC3

BC2

BC1

BC0

xxxxxxxx

RW

E69E

2

reserved

 

 

 

 

 

 

 

 

 

 

 

E6A0

1

EP0CS

Endpoint 0 Control and

HSNAK

0

0

0

0

0

BUSY

STALL

10000000

bbbbbbrb

 

 

 

Status

 

 

 

 

 

 

 

 

 

 

E6A1

1

EP1OUTCS

Endpoint 1 OUT Control

0

0

0

0

0

0

BUSY

STALL

00000000

bbbbbbrb

 

 

 

and Status

 

 

 

 

 

 

 

 

 

 

E6A2

1

EP1INCS

Endpoint 1 IN Control and

0

0

0

0

0

0

BUSY

STALL

00000000

bbbbbbrb

 

 

 

Status

 

 

 

 

 

 

 

 

 

 

E6A3

1

EP2CS

Endpoint 2 Control and

0

NPAK2

NPAK1

NPAK0

FULL

EMPTY

0

STALL

00101000

rrrrrrrb

 

 

 

Status

 

 

 

 

 

 

 

 

 

 

E6A4

1

EP4CS

Endpoint 4 Control and

0

0

NPAK1

NPAK0

FULL

EMPTY

0

STALL

00101000

rrrrrrrb

 

 

 

Status

 

 

 

 

 

 

 

 

 

 

E6A5

1

EP6CS

Endpoint 6 Control and

0

NPAK2

NPAK1

NPAK0

FULL

EMPTY

0

STALL

00000100

rrrrrrrb

 

 

 

Status

 

 

 

 

 

 

 

 

 

 

E6A6

1

EP8CS

Endpoint 8 Control and

0

0

NPAK1

NPAK0

FULL

EMPTY

0

STALL

00000100

rrrrrrrb

 

 

 

Status

 

 

 

 

 

 

 

 

 

 

E6A7

1

EP2FIFOFLGS

Endpoint 2 slave FIFO

0

0

0

0

0

PF

EF

FF

00000010

R

 

 

 

Flags

 

 

 

 

 

 

 

 

 

 

E6A8

1

EP4FIFOFLGS

Endpoint 4 slave FIFO

0

0

0

0

0

PF

EF

FF

00000010

R

 

 

 

Flags

 

 

 

 

 

 

 

 

 

 

E6A9

1

EP6FIFOFLGS

Endpoint 6 slave FIFO

0

0

0

0

0

PF

EF

FF

00000110

R

 

 

 

Flags

 

 

 

 

 

 

 

 

 

 

E6AA

1

EP8FIFOFLGS

Endpoint 8 slave FIFO

0

0

0

0

0

PF

EF

FF

00000110

R

 

 

 

Flags

 

 

 

 

 

 

 

 

 

 

E6AB

1

EP2FIFOBCH

Endpoint 2 slave FIFO

0

0

0

BC12

BC11

BC10

BC9

BC8

00000000

R

 

 

 

total byte count H

 

 

 

 

 

 

 

 

 

 

E6AC

1

EP2FIFOBCL

Endpoint 2 slave FIFO

BC7

BC6

BC5

BC4

BC3

BC2

BC1

BC0

00000000

R

 

 

 

total byte count L

 

 

 

 

 

 

 

 

 

 

E6AD

1

EP4FIFOBCH

Endpoint 4 slave FIFO

0

0

0

0

0

BC10

BC9

BC8

00000000

R

 

 

 

total byte count H

 

 

 

 

 

 

 

 

 

 

E6AE

1

EP4FIFOBCL

Endpoint 4 slave FIFO

BC7

BC6

BC5

BC4

BC3

BC2

BC1

BC0

00000000

R

 

 

 

total byte count L

 

 

 

 

 

 

 

 

 

 

E6AF

1

EP6FIFOBCH

Endpoint 6 slave FIFO

0

0

0

0

BC11

BC10

BC9

BC8

00000000

R

 

 

 

total byte count H

 

 

 

 

 

 

 

 

 

 

E6B0

1

EP6FIFOBCL

Endpoint 6 slave FIFO

BC7

BC6

BC5

BC4

BC3

BC2

BC1

BC0

00000000

R

 

 

 

total byte count L

 

 

 

 

 

 

 

 

 

 

E6B1

1

EP8FIFOBCH

Endpoint 8 slave FIFO

0

0

0

0

0

BC10

BC9

BC8

00000000

R

 

 

 

total byte count H

 

 

 

 

 

 

 

 

 

 

E6B2

1

EP8FIFOBCL

Endpoint 8 slave FIFO

BC7

BC6

BC5

BC4

BC3

BC2

BC1

BC0

00000000

R

 

 

 

total byte count L

 

 

 

 

 

 

 

 

 

 

E6B3

1

SUDPTRH

Setup Data Pointer high

A15

A14

A13

A12

A11

A10

A9

A8

xxxxxxxx

RW

 

 

 

address byte

 

 

 

 

 

 

 

 

 

 

E6B4

1

SUDPTRL

Setup Data Pointer low ad-

A7

A6

A5

A4

A3

A2

A1

0

xxxxxxx0

bbbbbbbr

 

 

 

dress byte

 

 

 

 

 

 

 

 

 

 

E6B5

1

SUDPTRCTL

Setup Data Pointer Auto

0

0

0

0

0

0

0

SDPAUTO

00000001

RW

 

 

 

Mode

 

 

 

 

 

 

 

 

 

 

 

2

reserved

 

 

 

 

 

 

 

 

 

 

 

E6B8

8

SET-UPDAT

8 bytes of setup data

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx

R

 

 

 

SET-UPDAT[0] =

 

 

 

 

 

 

 

 

 

 

 

 

 

bmRequestType

 

 

 

 

 

 

 

 

 

 

 

 

 

SET-UPDAT[1] =

 

 

 

 

 

 

 

 

 

 

 

 

 

bmRequest

 

 

 

 

 

 

 

 

 

 

 

 

 

SET-UPDAT[2:3] = wVal-

 

 

 

 

 

 

 

 

 

 

 

 

 

ue

 

 

 

 

 

 

 

 

 

 

 

 

 

SET-UPDAT[4:5] = wInd-

 

 

 

 

 

 

 

 

 

 

 

 

 

ex

 

 

 

 

 

 

 

 

 

 

 

 

 

SET-UPDAT[6:7] =

 

 

 

 

 

 

 

 

 

 

 

 

 

wLength

 

 

 

 

 

 

 

 

 

 

 

 

GPIF

 

 

 

 

 

 

 

 

 

 

 

E6C0

1

GPIFWFSELECT

Waveform Selector

SINGLEWR1

SINGLEWR0

SINGLERD1

SINGLERD0

FIFOWR1

FIFOWR0

FIFORD1

FIFORD0

11100100

RW

E6C1

1

GPIFIDLECS

GPIF Done, GPIF IDLE

DONE

0

0

0

0

0

0

IDLEDRV

10000000

RW

 

 

 

drive mode

 

 

 

 

 

 

 

 

 

 

E6C2

1

GPIFIDLECTL

Inactive Bus, CTL states

0

0

CTL5

CTL4

CTL3

CTL2

CTL1

CTL0

11111111

RW

E6C3

1

GPIFCTLCFG

CTL Drive Type

TRICTL

0

CTL5

CTL4

CTL3

CTL2

CTL1

CTL0

00000000

RW

E6C4

1

GPIFADRH[11]

GPIF Address H

0

0

0

0

0

0

0

GPIFA8

00000000

RW

E6C5

1

GPIFADRL[11]

GPIF Address L

GPIFA7

GPIFA6

GPIFA5

GPIFA4

GPIFA3

GPIFA2

GPIFA1

GPIFA0

00000000

RW

 

 

FLOWSTATE

 

 

 

 

 

 

 

 

 

 

 

E6C6

1

FLOWSTATE

Flowstate Enable and

FSE

0

0

0

0

FS2

FS1

FS0

00000000

brrrrbbb

 

 

 

Selector

 

 

 

 

 

 

 

 

 

 

E6C7

1

FLOWLOGIC

Flowstate Logic

LFUNC1

LFUNC0

TERMA2

TERMA1

TERMA0

TERMB2

TERMB1

TERMB0

00000000

RW

E6C8

1

FLOWEQ0CTL

CTL-Pin States in

CTL0E3

CTL0E2

CTL0E1/

CTL0E0/

CTL3

CTL2

CTL1

CTL0

00000000

RW

 

 

 

Flowstate

 

 

CTL5

CTL4

 

 

 

 

 

 

 

 

 

(when Logic = 0)

 

 

 

 

 

 

 

 

 

 

E6C9

1

FLOWEQ1CTL

CTL-Pin States in Flow-

CTL0E3

CTL0E2

CTL0E1/

CTL0E0/

CTL3

CTL2

CTL1

CTL0

00000000

RW

 

 

 

state (when Logic = 1)

 

 

CTL5

CTL4

 

 

 

 

 

 

E6CA

1

FLOWHOLDOFF

Holdoff Configuration

HOPERIOD3

HOPERIOD2

HOPERIOD1

HOPERIOD

HOSTATE

HOCTL2

HOCTL1

HOCTL0

00010010

RW

 

 

 

 

 

 

 

0

 

 

 

 

 

 

Document #: 38-08032 Rev. *L

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Contents Features CY7C68013A/14A/15A/16A Cypress Semiconductor Corporation 198 Champion CourtFeatures CY7C68015A/16A only Logic Block DiagramFeatures CY7C68013A/14A only Applications Functional OverviewUSB Boot Methods Bus-powered ApplicationsReNumeration Interrupt SystemFIFO/GPIF Interrupt INT4 INT2 USB InterruptsPriority INT2VEC Value Source Reset and Wakeup Reset PinReset Timing Values Condition Program/Data RAMInside FX2LP Outside FX2LP Internal Code Memory, EA =Register Addresses External Code Memory, EA =Setup Data Buffer Endpoint Configurations High -speed ModeEndpoint RAM Size × 64 bytes Endpoints 0 × 512 bytes12.5 Default Full-Speed Alternate Settings Master/Slave Control SignalsExternal Fifo Interface ArchitectureAutopointer Access ECC Generation7Gpif USB Uploads and Downloads18 I2C Controller Compatible with Previous Generation EZ-USB FX2Part Number Conversion Table Package DescriptionPin Assignments 20 CY7C68013A/14A and CY7C68015A/16A DifferencesIfclk PE0 PE1128 CY7C68013A/CY7C68014A Pin TqfpCY7C68013A/CY7C68014A CY7C68013A/CY7C68014A 56-pin Ssop CY7C68013A/CY7C68014A 56-pin Ssop Pin AssignmentCY7C68015A/CY7C68016A Pin QFN CY7C68013A 56-pin Vfbga Pin Assignment Top View FX2LP Pin Descriptions 128 100 56 VF Name Type Default CY7C68013A/15A Pin DescriptionsPort 56 VF Name Type Default DescriptionFX2LP Pin Descriptions IFCONFIG1..0 WU2FIFOADR0 FIFOADR1GPIFADR0 PORTCCFG.0GPIFADR1 PORTCCFG.1Port E T0OUTT1OUT T2OUTRXD1OUT INT6T2EX GPIFADR8Flagb FlagcCTL3 CTL4Ground Register Summary FX2LP Register SummaryRegister can only be reset, it cannot be set Epie EP0CS E6CB Flowstb DPL0 = both read/write bit Thermal Characteristics Absolute Maximum RatingsOperating Conditions ΘJc + θCaUSB Transceiver DC CharacteristicsAC Electrical Characteristics Program Memory Read Parameters Description Min Typ Max Unit Program Memory ReadClkout Data Memory Read Parameters Description Min Typ Max Unit Data Memory ReadCLKOUT17 Data Memory Write Parameters Description Min Max Unit Data Memory WriteStretch = Portc Strobe Feature Timings WR# Strobe Function when Portc is Accessed byGpif Synchronous Signals Gpif Synchronous Signals Timing Diagram20Slave Fifo Synchronous Read Timing Diagram20 Slave Fifo Synchronous ReadSlave Fifo Asynchronous Read Timing Diagram20 Slave Fifo Asynchronous ReadSlave Fifo Synchronous Write Timing Diagram20 Slave Fifo Synchronous WriteSlave Fifo Asynchronous Write Slave Fifo Synchronous Packet End StrobeSlave Fifo Synchronous Write Sequence and Timing Diagram Slave Fifo Asynchronous Packet End StrobeSlave Fifo Output Enable Slave Fifo Address to Flags/DataFIFOADR10 to SLRD/SLWR/PKTEND Setup Time Slave Fifo Synchronous AddressSlave Fifo Asynchronous Address RD/WR/PKTEND to FIFOADR10 Hold TimeSequence Diagram Single and Burst Synchronous Read Example10.17.2 Single and Burst Synchronous Write Sequence Diagram of a Single and Burst Asynchronous Read Slave Fifo Asynchronous Read Sequence and Timing Diagram20Sequence Diagram of a Single and Burst Asynchronous Write Slave Fifo Asynchronous Write Sequence and Timing Diagram20Ideal for battery powered applications Ideal for non-battery powered applicationsOrdering Information Development Tool KitPackage Diagrams Lead Shrunk Small Outline Package O56Lead QFN 8 x 8 mm LF56A Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A100RA Lead Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A128 PCB Layout Recommendations Vfbga 5 x 5 x 1.0 mm 0.50 Pitch, 0.30 Ball BZ56Quad Flat Package No Leads QFN Package Design Notes Cross-section of the Area Underneath the QFN PackageIssue Orig. Description of Change Date Cmcc Pyrs

CY7C68016A, CY7C68014A, CY7C68015A, CY7C68013 specifications

The Cypress CY7C68013, CY7C68015A, CY7C68014A, and CY7C68016A are part of Cypress Semiconductor's EZ-USB family of microcontrollers, known for their high performance and flexibility in USB applications. These devices are primarily used for USB interfacing and have gained popularity in various industries due to their robust features and capabilities.

One of the main features of the CY7C68013 is its Dual FIFO architecture, allowing for efficient data transfer between USB and the system memory. This feature optimizes throughput and reduces CPU overhead, making it an excellent choice for applications that require high-speed data exchange, such as video streaming, data acquisition, and industrial automation. The device is equipped with a USB 2.0 interface which supports full-speed operation at 12 Mbps, ensuring compatibility with a wide range of USB devices.

The CY7C68015A, a similar variant, offers additional memory options, providing users with the flexibility to select the necessary capacity for their specific applications. This part is particularly useful in scenarios that demand more users or higher data storage, making it ideal for complex USB peripherals like printers and multifunction devices. Moreover, it includes a unique capability of upgradeable firmware, ensuring that the device remains relevant and functional as technology evolves.

In contrast, the CY7C68014A stands out with its support for isochronous data transfers, making it suitable for real-time applications that require timely data delivery. This is particularly important in audio and video applications where delays can impact performance. The device incorporates advanced power management features, allowing it to operate efficiently both in low and high-power modes.

Lastly, the CY7C68016A integrates enhanced security features, positioning it as an ideal choice for applications that require data integrity and protection against unauthorized access. It supports various encryption standards and provides secure boot capabilities, making it suitable for secure environments such as financial transactions and sensitive data processing.

In summary, the CY7C68013, CY7C68015A, CY7C68014A, and CY7C68016A microcontrollers offer a versatile suite of features that cater to a wide array of USB applications. Their design emphasizes performance, flexibility, and security, making them essential components in today's rapidly evolving technology landscape. Whether in consumer electronics, industrial automation, or specialized applications, these devices provide the reliability and efficiency that engineers and developers require.