Cypress CY7C68014A, CY7C68013, CY7C68015A WU2, FIFOADR0, IFCONFIG1..0, FIFOADR1, Pktend, Slcs#

Page 23

 

 

 

 

 

 

 

 

 

 

 

CY7C68013A, CY7C68014A

 

 

 

 

 

 

 

 

 

 

 

CY7C68015A, CY7C68016A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 11. FX2LP Pin Descriptions (continued)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

128

 

100

56

56

56 VF-

Name

Type

Default

Description

 

 

TQFP

TQFP

SSOP

QFN

BGA

 

 

 

 

 

 

 

85

 

70

43

36

7F

PA3 or

IO/Z

I

Multiplexed pin whose function is selected by:

 

 

 

 

 

 

 

 

 

 

WU2

 

(PA3)

WAKEUP.7 and OEA.3

 

 

 

 

 

 

 

 

 

 

 

 

PA3 is a bidirectional IO port pin.

 

 

 

 

 

 

 

 

 

 

 

 

WU2 is an alternate source for USB Wakeup, enabled

 

 

 

 

 

 

 

 

 

 

 

 

by WU2EN bit (WAKEUP.1) and polarity set by

 

 

 

 

 

 

 

 

 

 

 

 

WU2POL (WAKEUP.4). If the 8051 is in suspend and

 

 

 

 

 

 

 

 

 

 

 

 

WU2EN = 1, a transition on this pin starts up the oscil-

 

 

 

 

 

 

 

 

 

 

 

 

lator and interrupts the 8051 to enable it to exit the

 

 

 

 

 

 

 

 

 

 

 

 

suspend mode. Asserting this pin inhibits the chip from

 

 

 

 

 

 

 

 

 

 

 

 

suspending, if WU2EN = 1.

 

89

 

71

44

37

6F

PA4 or

IO/Z

I

Multiplexed pin whose function is selected by:

 

 

 

 

 

 

 

 

 

 

FIFOADR0

 

(PA4)

IFCONFIG[1..0].

 

 

 

 

 

 

 

 

 

 

 

 

PA4 is a bidirectional IO port pin.

 

 

 

 

 

 

 

 

 

 

 

 

FIFOADR0 is an input-only address select for the slave

 

 

 

 

 

 

 

 

 

 

 

 

FIFOs connected to FD[7..0] or FD[15..0].

 

90

 

72

45

38

8C

PA5 or

IO/Z

I

Multiplexed pin whose function is selected by:

 

 

 

 

 

 

 

 

 

 

FIFOADR1

 

(PA5)

IFCONFIG[1..0].

 

 

 

 

 

 

 

 

 

 

 

 

PA5 is a bidirectional IO port pin.

 

 

 

 

 

 

 

 

 

 

 

 

FIFOADR1 is an input-only address select for the slave

 

 

 

 

 

 

 

 

 

 

 

 

FIFOs connected to FD[7..0] or FD[15..0].

 

91

 

73

46

39

7C

PA6 or

IO/Z

I

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

 

PKTEND

 

(PA6)

IFCONFIG[1:0] bits.

 

 

 

 

 

 

 

 

 

 

 

 

PA6 is a bidirectional IO port pin.

 

 

 

 

 

 

 

 

 

 

 

 

PKTEND is an input used to commit the FIFO packet

 

 

 

 

 

 

 

 

 

 

 

 

data to the endpoint and whose polarity is program-

 

 

 

 

 

 

 

 

 

 

 

 

mable via FIFOPINPOLAR.5.

 

92

 

74

47

40

6C

PA7 or

IO/Z

I

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

 

FLAGD or

 

(PA7)

IFCONFIG[1:0] and PORTACFG.7 bits.

 

 

 

 

 

 

 

 

 

SLCS#

 

 

PA7 is a bidirectional IO port pin.

 

 

 

 

 

 

 

 

 

 

 

 

FLAGD is a programmable slave-FIFO output status

 

 

 

 

 

 

 

 

 

 

 

 

flag signal.

 

 

 

 

 

 

 

 

 

 

 

 

SLCS# gates all other slave FIFO enable/strobes

 

Port

B

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

44

 

34

25

18

3H

PB0 or

IO/Z

I

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

 

FD[0]

 

(PB0)

following bits: IFCONFIG[1..0].

 

 

 

 

 

 

 

 

 

 

 

 

PB0 is a bidirectional IO port pin.

 

 

 

 

 

 

 

 

 

 

 

 

FD[0] is the bidirectional FIFO/GPIF data bus.

 

45

 

35

26

19

4F

PB1 or

IO/Z

I

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

 

FD[1]

 

(PB1)

following bits: IFCONFIG[1..0].

 

 

 

 

 

 

 

 

 

 

 

 

PB1 is a bidirectional IO port pin.

 

 

 

 

 

 

 

 

 

 

 

 

FD[1] is the bidirectional FIFO/GPIF data bus.

 

46

 

36

27

20

4H

PB2 or

IO/Z

I

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

 

FD[2]

 

(PB2)

following bits: IFCONFIG[1..0].

 

 

 

 

 

 

 

 

 

 

 

 

PB2 is a bidirectional IO port pin.

 

 

 

 

 

 

 

 

 

 

 

 

FD[2] is the bidirectional FIFO/GPIF data bus.

 

47

 

37

28

21

4G

PB3 or

IO/Z

I

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

 

FD[3]

 

(PB3)

following bits: IFCONFIG[1..0].

 

 

 

 

 

 

 

 

 

 

 

 

PB3 is a bidirectional IO port pin.

 

 

 

 

 

 

 

 

 

 

 

 

FD[3] is the bidirectional FIFO/GPIF data bus.

 

54

 

44

29

22

5H

PB4 or

IO/Z

I

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

 

FD[4]

 

(PB4)

following bits: IFCONFIG[1..0].

 

 

 

 

 

 

 

 

 

 

 

 

PB4 is a bidirectional IO port pin.

 

 

 

 

 

 

 

 

 

 

 

 

FD[4] is the bidirectional FIFO/GPIF data bus.

 

Document #: 38-08032 Rev. *L

 

 

 

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Contents Cypress Semiconductor Corporation 198 Champion Court Features CY7C68013A/14A/15A/16AFeatures CY7C68015A/16A only Logic Block DiagramFeatures CY7C68013A/14A only Functional Overview ApplicationsInterrupt System USB Boot MethodsBus-powered Applications ReNumerationFIFO/GPIF Interrupt INT4 INT2 USB InterruptsPriority INT2VEC Value Source Reset Pin Reset and WakeupProgram/Data RAM Reset Timing Values ConditionInternal Code Memory, EA = Inside FX2LP Outside FX2LPExternal Code Memory, EA = Register AddressesSize × 64 bytes Endpoints 0 × 512 bytes Setup Data BufferEndpoint Configurations High -speed Mode Endpoint RAMArchitecture 12.5 Default Full-Speed Alternate SettingsMaster/Slave Control Signals External Fifo InterfaceUSB Uploads and Downloads Autopointer AccessECC Generation7 GpifPackage Description 18 I2C ControllerCompatible with Previous Generation EZ-USB FX2 Part Number Conversion TablePE1 Pin Assignments20 CY7C68013A/14A and CY7C68015A/16A Differences Ifclk PE0128 Pin Tqfp CY7C68013A/CY7C68014ACY7C68013A/CY7C68014A CY7C68013A/CY7C68014A 56-pin Ssop Pin Assignment CY7C68013A/CY7C68014A 56-pin SsopCY7C68015A/CY7C68016A Pin QFN CY7C68013A 56-pin Vfbga Pin Assignment Top View CY7C68013A/15A Pin Descriptions FX2LP Pin Descriptions 128 100 56 VF Name Type DefaultPort 56 VF Name Type Default DescriptionFX2LP Pin Descriptions FIFOADR1 IFCONFIG1..0WU2 FIFOADR0PORTCCFG.1 GPIFADR0PORTCCFG.0 GPIFADR1T2OUT Port ET0OUT T1OUTGPIFADR8 RXD1OUTINT6 T2EXCTL4 FlagbFlagc CTL3Ground FX2LP Register Summary Register SummaryRegister can only be reset, it cannot be set Epie EP0CS E6CB Flowstb DPL0 = both read/write bit ΘJc + θCa Thermal CharacteristicsAbsolute Maximum Ratings Operating ConditionsUSB Transceiver DC CharacteristicsAC Electrical Characteristics Program Memory Read Parameters Description Min Typ Max Unit Program Memory ReadClkout Data Memory Read Parameters Description Min Typ Max Unit Data Memory ReadCLKOUT17 Data Memory Write Parameters Description Min Max Unit Data Memory WriteStretch = WR# Strobe Function when Portc is Accessed by Portc Strobe Feature TimingsGpif Synchronous Signals Timing Diagram20 Gpif Synchronous SignalsSlave Fifo Synchronous Read Slave Fifo Synchronous Read Timing Diagram20Slave Fifo Asynchronous Read Slave Fifo Asynchronous Read Timing Diagram20Slave Fifo Synchronous Write Slave Fifo Synchronous Write Timing Diagram20Slave Fifo Synchronous Packet End Strobe Slave Fifo Asynchronous WriteSlave Fifo Asynchronous Packet End Strobe Slave Fifo Synchronous Write Sequence and Timing DiagramSlave Fifo Address to Flags/Data Slave Fifo Output EnableRD/WR/PKTEND to FIFOADR10 Hold Time FIFOADR10 to SLRD/SLWR/PKTEND Setup TimeSlave Fifo Synchronous Address Slave Fifo Asynchronous AddressSingle and Burst Synchronous Read Example Sequence Diagram10.17.2 Single and Burst Synchronous Write Slave Fifo Asynchronous Read Sequence and Timing Diagram20 Sequence Diagram of a Single and Burst Asynchronous ReadSlave Fifo Asynchronous Write Sequence and Timing Diagram20 Sequence Diagram of a Single and Burst Asynchronous WriteDevelopment Tool Kit Ideal for battery powered applicationsIdeal for non-battery powered applications Ordering InformationLead Shrunk Small Outline Package O56 Package DiagramsLead QFN 8 x 8 mm LF56A Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A100RA Lead Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A128 Vfbga 5 x 5 x 1.0 mm 0.50 Pitch, 0.30 Ball BZ56 PCB Layout RecommendationsCross-section of the Area Underneath the QFN Package Quad Flat Package No Leads QFN Package Design NotesIssue Orig. Description of Change Date Pyrs Cmcc

CY7C68016A, CY7C68014A, CY7C68015A, CY7C68013 specifications

The Cypress CY7C68013, CY7C68015A, CY7C68014A, and CY7C68016A are part of Cypress Semiconductor's EZ-USB family of microcontrollers, known for their high performance and flexibility in USB applications. These devices are primarily used for USB interfacing and have gained popularity in various industries due to their robust features and capabilities.

One of the main features of the CY7C68013 is its Dual FIFO architecture, allowing for efficient data transfer between USB and the system memory. This feature optimizes throughput and reduces CPU overhead, making it an excellent choice for applications that require high-speed data exchange, such as video streaming, data acquisition, and industrial automation. The device is equipped with a USB 2.0 interface which supports full-speed operation at 12 Mbps, ensuring compatibility with a wide range of USB devices.

The CY7C68015A, a similar variant, offers additional memory options, providing users with the flexibility to select the necessary capacity for their specific applications. This part is particularly useful in scenarios that demand more users or higher data storage, making it ideal for complex USB peripherals like printers and multifunction devices. Moreover, it includes a unique capability of upgradeable firmware, ensuring that the device remains relevant and functional as technology evolves.

In contrast, the CY7C68014A stands out with its support for isochronous data transfers, making it suitable for real-time applications that require timely data delivery. This is particularly important in audio and video applications where delays can impact performance. The device incorporates advanced power management features, allowing it to operate efficiently both in low and high-power modes.

Lastly, the CY7C68016A integrates enhanced security features, positioning it as an ideal choice for applications that require data integrity and protection against unauthorized access. It supports various encryption standards and provides secure boot capabilities, making it suitable for secure environments such as financial transactions and sensitive data processing.

In summary, the CY7C68013, CY7C68015A, CY7C68014A, and CY7C68016A microcontrollers offer a versatile suite of features that cater to a wide array of USB applications. Their design emphasizes performance, flexibility, and security, making them essential components in today's rapidly evolving technology landscape. Whether in consumer electronics, industrial automation, or specialized applications, these devices provide the reliability and efficiency that engineers and developers require.
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