Cypress CY7C68014A, CY7C68013, CY7C68015A, CY7C68016A manual = both read/write bit

Page 35

CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Table 12. FX2LP Register Summary (continued)

Hex

Size

Name

Description

b7

b6

b5

b4

b3

b2

b1

b0

Default

Access

BE

1

GPIFSGLDATLX[13]

GPIF Data L w/ Trigger

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx

RW

BF

1

GPIFSGLDATL-

GPIF Data L w/ No Trigger

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx

R

 

 

NOX[13]

 

 

 

 

 

 

 

 

 

 

 

C0

1

SCON1[13]

Serial Port 1 Control (bit

SM0_1

SM1_1

SM2_1

REN_1

TB8_1

RB8_1

TI_1

RI_1

00000000

RW

 

 

 

addressable)

 

 

 

 

 

 

 

 

 

 

C1

1

SBUF1[13]

Serial Port 1 Data Buffer

D7

D6

D5

D4

D3

D2

D1

D0

00000000

RW

C2

6

reserved

 

 

 

 

 

 

 

 

 

 

 

C8

1

T2CON

Timer/Counter 2 Control

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

CT2

CPRL2

00000000

RW

 

 

 

(bit addressable)

 

 

 

 

 

 

 

 

 

 

C9

1

reserved

 

 

 

 

 

 

 

 

 

 

 

CA

1

RCAP2L

Capture for Timer 2, au-

D7

D6

D5

D4

D3

D2

D1

D0

00000000

RW

 

 

 

to-reload, up-counter

 

 

 

 

 

 

 

 

 

 

CB

1

RCAP2H

Capture for Timer 2, au-

D7

D6

D5

D4

D3

D2

D1

D0

00000000

RW

 

 

 

to-reload, up-counter

 

 

 

 

 

 

 

 

 

 

CC

1

TL2

Timer 2 reload L

D7

D6

D5

D4

D3

D2

D1

D0

00000000

RW

CD

1

TH2

Timer 2 reload H

D15

D14

D13

D12

D11

D10

D9

D8

00000000

RW

CE

2

reserved

 

 

 

 

 

 

 

 

 

 

 

D0

1

PSW

Program Status Word (bit

CY

AC

F0

RS1

RS0

OV

F1

P

00000000

RW

 

 

 

addressable)

 

 

 

 

 

 

 

 

 

 

D1

7

reserved

 

 

 

 

 

 

 

 

 

 

 

D8

1

EICON[13]

External Interrupt Control

SMOD1

1

ERESI

RESI

INT6

0

0

0

01000000

RW

D9

7

reserved

 

 

 

 

 

 

 

 

 

 

 

E0

1

ACC

Accumulator (bit address-

D7

D6

D5

D4

D3

D2

D1

D0

00000000

RW

 

 

 

able)

 

 

 

 

 

 

 

 

 

 

E1

7

reserved

 

 

 

 

 

 

 

 

 

 

 

E8

1

EIE[13]

External Interrupt En-

1

1

1

EX6

EX5

EX4

EI²C

EUSB

11100000

RW

 

 

 

able(s)

 

 

 

 

 

 

 

 

 

 

E9

7

reserved

 

 

 

 

 

 

 

 

 

 

 

F0

1

B

B (bit addressable)

D7

D6

D5

D4

D3

D2

D1

D0

00000000

RW

F1

7

reserved

 

 

 

 

 

 

 

 

 

 

 

F8

1

EIP[13]

External Interrupt Priority

1

1

1

PX6

PX5

PX4

PI²C

PUSB

11100000

RW

 

 

 

Control

 

 

 

 

 

 

 

 

 

 

F9

7

reserved

 

 

 

 

 

 

 

 

 

 

 

R = all bits read-only

W = all bits write-only

r = read-only bit w = write-only bit

b = both read/write bit

Document #: 38-08032 Rev. *L

Page 35 of 62

[+] Feedback

Page 34 Page 36
Image 35
Page 34 Page 36
Contents Cypress Semiconductor Corporation 198 Champion Court Features CY7C68013A/14A/15A/16AFeatures CY7C68015A/16A only Logic Block DiagramFeatures CY7C68013A/14A only Functional Overview ApplicationsInterrupt System USB Boot MethodsBus-powered Applications ReNumerationFIFO/GPIF Interrupt INT4 INT2 USB InterruptsPriority INT2VEC Value Source Reset Pin Reset and WakeupProgram/Data RAM Reset Timing Values ConditionInternal Code Memory, EA = Inside FX2LP Outside FX2LPExternal Code Memory, EA = Register AddressesSize × 64 bytes Endpoints 0 × 512 bytes Setup Data BufferEndpoint Configurations High -speed Mode Endpoint RAMArchitecture 12.5 Default Full-Speed Alternate SettingsMaster/Slave Control Signals External Fifo InterfaceUSB Uploads and Downloads Autopointer AccessECC Generation7 GpifPackage Description 18 I2C ControllerCompatible with Previous Generation EZ-USB FX2 Part Number Conversion TablePE1 Pin Assignments20 CY7C68013A/14A and CY7C68015A/16A Differences Ifclk PE0128 Pin Tqfp CY7C68013A/CY7C68014ACY7C68013A/CY7C68014A CY7C68013A/CY7C68014A 56-pin Ssop Pin Assignment CY7C68013A/CY7C68014A 56-pin SsopCY7C68015A/CY7C68016A Pin QFN CY7C68013A 56-pin Vfbga Pin Assignment Top View CY7C68013A/15A Pin Descriptions FX2LP Pin Descriptions 128 100 56 VF Name Type DefaultPort 56 VF Name Type Default DescriptionFX2LP Pin Descriptions FIFOADR1 IFCONFIG1..0WU2 FIFOADR0PORTCCFG.1 GPIFADR0PORTCCFG.0 GPIFADR1T2OUT Port ET0OUT T1OUTGPIFADR8 RXD1OUTINT6 T2EXCTL4 FlagbFlagc CTL3Ground FX2LP Register Summary Register SummaryRegister can only be reset, it cannot be set Epie EP0CS E6CB Flowstb DPL0 = both read/write bit ΘJc + θCa Thermal CharacteristicsAbsolute Maximum Ratings Operating ConditionsUSB Transceiver DC CharacteristicsAC Electrical Characteristics Program Memory Read Parameters Description Min Typ Max Unit Program Memory ReadClkout Data Memory Read Parameters Description Min Typ Max Unit Data Memory ReadCLKOUT17 Data Memory Write Parameters Description Min Max Unit Data Memory WriteStretch = WR# Strobe Function when Portc is Accessed by Portc Strobe Feature TimingsGpif Synchronous Signals Timing Diagram20 Gpif Synchronous SignalsSlave Fifo Synchronous Read Slave Fifo Synchronous Read Timing Diagram20Slave Fifo Asynchronous Read Slave Fifo Asynchronous Read Timing Diagram20Slave Fifo Synchronous Write Slave Fifo Synchronous Write Timing Diagram20Slave Fifo Synchronous Packet End Strobe Slave Fifo Asynchronous WriteSlave Fifo Asynchronous Packet End Strobe Slave Fifo Synchronous Write Sequence and Timing DiagramSlave Fifo Address to Flags/Data Slave Fifo Output EnableRD/WR/PKTEND to FIFOADR10 Hold Time FIFOADR10 to SLRD/SLWR/PKTEND Setup TimeSlave Fifo Synchronous Address Slave Fifo Asynchronous AddressSingle and Burst Synchronous Read Example Sequence Diagram10.17.2 Single and Burst Synchronous Write Slave Fifo Asynchronous Read Sequence and Timing Diagram20 Sequence Diagram of a Single and Burst Asynchronous ReadSlave Fifo Asynchronous Write Sequence and Timing Diagram20 Sequence Diagram of a Single and Burst Asynchronous WriteDevelopment Tool Kit Ideal for battery powered applicationsIdeal for non-battery powered applications Ordering InformationLead Shrunk Small Outline Package O56 Package DiagramsLead QFN 8 x 8 mm LF56A Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A100RA Lead Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A128 Vfbga 5 x 5 x 1.0 mm 0.50 Pitch, 0.30 Ball BZ56 PCB Layout RecommendationsCross-section of the Area Underneath the QFN Package Quad Flat Package No Leads QFN Package Design NotesIssue Orig. Description of Change Date Pyrs Cmcc

CY7C68016A, CY7C68014A, CY7C68015A, CY7C68013 specifications

The Cypress CY7C68013, CY7C68015A, CY7C68014A, and CY7C68016A are part of Cypress Semiconductor's EZ-USB family of microcontrollers, known for their high performance and flexibility in USB applications. These devices are primarily used for USB interfacing and have gained popularity in various industries due to their robust features and capabilities.

One of the main features of the CY7C68013 is its Dual FIFO architecture, allowing for efficient data transfer between USB and the system memory. This feature optimizes throughput and reduces CPU overhead, making it an excellent choice for applications that require high-speed data exchange, such as video streaming, data acquisition, and industrial automation. The device is equipped with a USB 2.0 interface which supports full-speed operation at 12 Mbps, ensuring compatibility with a wide range of USB devices.

The CY7C68015A, a similar variant, offers additional memory options, providing users with the flexibility to select the necessary capacity for their specific applications. This part is particularly useful in scenarios that demand more users or higher data storage, making it ideal for complex USB peripherals like printers and multifunction devices. Moreover, it includes a unique capability of upgradeable firmware, ensuring that the device remains relevant and functional as technology evolves.

In contrast, the CY7C68014A stands out with its support for isochronous data transfers, making it suitable for real-time applications that require timely data delivery. This is particularly important in audio and video applications where delays can impact performance. The device incorporates advanced power management features, allowing it to operate efficiently both in low and high-power modes.

Lastly, the CY7C68016A integrates enhanced security features, positioning it as an ideal choice for applications that require data integrity and protection against unauthorized access. It supports various encryption standards and provides secure boot capabilities, making it suitable for secure environments such as financial transactions and sensitive data processing.

In summary, the CY7C68013, CY7C68015A, CY7C68014A, and CY7C68016A microcontrollers offer a versatile suite of features that cater to a wide array of USB applications. Their design emphasizes performance, flexibility, and security, making them essential components in today's rapidly evolving technology landscape. Whether in consumer electronics, industrial automation, or specialized applications, these devices provide the reliability and efficiency that engineers and developers require.
Top Page Image Contents