Cypress CY7C68013, CY7C68015A manual Slave Fifo Output Enable, Slave Fifo Address to Flags/Data

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CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

10.13 Slave FIFO Output Enable

Figure 25. Slave FIFO Output Enable Timing Diagram[20]

SLOE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DATA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tOEon

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tOEoff

Table 29. Slave FIFO Output Enable Parameters

Parameter

Description

Min

Max

Unit

tOEon

SLOE Assert to FIFO DATA Output

 

10.5

ns

tOEoff

SLOE Deassert to FIFO DATA Hold

 

10.5

ns

10.14 Slave FIFO Address to Flags/Data

Figure 26. Slave FIFO Address to Flags/Data Timing Diagram[20]

FIFOADR [1.0]

tXFLG

FLAGS

tXFD

DATA

N

 

 

N+1

Table 30. Slave FIFO Address to Flags/Data Parameters

Parameter

Description

Min

Max

Unit

tXFLG

FIFOADR[1:0] to FLAGS Output Propagation Delay

 

10.7

ns

tXFD

FIFOADR[1:0] to FIFODATA Output Propagation Delay

 

14.3

ns

Document #: 38-08032 Rev. *L

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Contents Features CY7C68013A/14A/15A/16A Cypress Semiconductor Corporation 198 Champion CourtLogic Block Diagram Features CY7C68013A/14A onlyFeatures CY7C68015A/16A only Applications Functional OverviewUSB Boot Methods Bus-powered ApplicationsReNumeration Interrupt SystemINT2 USB Interrupts Priority INT2VEC Value SourceFIFO/GPIF Interrupt INT4 Reset and Wakeup Reset PinReset Timing Values Condition Program/Data RAMInside FX2LP Outside FX2LP Internal Code Memory, EA =Register Addresses External Code Memory, EA =Setup Data Buffer Endpoint Configurations High -speed ModeEndpoint RAM Size × 64 bytes Endpoints 0 × 512 bytes12.5 Default Full-Speed Alternate Settings Master/Slave Control SignalsExternal Fifo Interface ArchitectureAutopointer Access ECC Generation7Gpif USB Uploads and Downloads18 I2C Controller Compatible with Previous Generation EZ-USB FX2Part Number Conversion Table Package DescriptionPin Assignments 20 CY7C68013A/14A and CY7C68015A/16A DifferencesIfclk PE0 PE1128 CY7C68013A/CY7C68014A Pin TqfpCY7C68013A/CY7C68014A CY7C68013A/CY7C68014A 56-pin Ssop CY7C68013A/CY7C68014A 56-pin Ssop Pin AssignmentCY7C68015A/CY7C68016A Pin QFN CY7C68013A 56-pin Vfbga Pin Assignment Top View FX2LP Pin Descriptions 128 100 56 VF Name Type Default CY7C68013A/15A Pin Descriptions56 VF Name Type Default Description FX2LP Pin DescriptionsPort IFCONFIG1..0 WU2FIFOADR0 FIFOADR1GPIFADR0 PORTCCFG.0GPIFADR1 PORTCCFG.1Port E T0OUTT1OUT T2OUTRXD1OUT INT6T2EX GPIFADR8Flagb FlagcCTL3 CTL4Ground Register Summary FX2LP Register SummaryRegister can only be reset, it cannot be set Epie EP0CS E6CB Flowstb DPL0 = both read/write bit Thermal Characteristics Absolute Maximum RatingsOperating Conditions ΘJc + θCaDC Characteristics AC Electrical CharacteristicsUSB Transceiver Program Memory Read ClkoutProgram Memory Read Parameters Description Min Typ Max Unit Data Memory Read CLKOUT17Data Memory Read Parameters Description Min Typ Max Unit Data Memory Write Stretch =Data Memory Write Parameters Description Min Max Unit Portc Strobe Feature Timings WR# Strobe Function when Portc is Accessed byGpif Synchronous Signals Gpif Synchronous Signals Timing Diagram20Slave Fifo Synchronous Read Timing Diagram20 Slave Fifo Synchronous ReadSlave Fifo Asynchronous Read Timing Diagram20 Slave Fifo Asynchronous ReadSlave Fifo Synchronous Write Timing Diagram20 Slave Fifo Synchronous WriteSlave Fifo Asynchronous Write Slave Fifo Synchronous Packet End StrobeSlave Fifo Synchronous Write Sequence and Timing Diagram Slave Fifo Asynchronous Packet End StrobeSlave Fifo Output Enable Slave Fifo Address to Flags/DataFIFOADR10 to SLRD/SLWR/PKTEND Setup Time Slave Fifo Synchronous AddressSlave Fifo Asynchronous Address RD/WR/PKTEND to FIFOADR10 Hold TimeSequence Diagram Single and Burst Synchronous Read Example10.17.2 Single and Burst Synchronous Write Sequence Diagram of a Single and Burst Asynchronous Read Slave Fifo Asynchronous Read Sequence and Timing Diagram20Sequence Diagram of a Single and Burst Asynchronous Write Slave Fifo Asynchronous Write Sequence and Timing Diagram20Ideal for battery powered applications Ideal for non-battery powered applicationsOrdering Information Development Tool KitPackage Diagrams Lead Shrunk Small Outline Package O56Lead QFN 8 x 8 mm LF56A Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A100RA Lead Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A128 PCB Layout Recommendations Vfbga 5 x 5 x 1.0 mm 0.50 Pitch, 0.30 Ball BZ56Quad Flat Package No Leads QFN Package Design Notes Cross-section of the Area Underneath the QFN PackageIssue Orig. Description of Change Date Cmcc Pyrs

CY7C68016A, CY7C68014A, CY7C68015A, CY7C68013 specifications

The Cypress CY7C68013, CY7C68015A, CY7C68014A, and CY7C68016A are part of Cypress Semiconductor's EZ-USB family of microcontrollers, known for their high performance and flexibility in USB applications. These devices are primarily used for USB interfacing and have gained popularity in various industries due to their robust features and capabilities.

One of the main features of the CY7C68013 is its Dual FIFO architecture, allowing for efficient data transfer between USB and the system memory. This feature optimizes throughput and reduces CPU overhead, making it an excellent choice for applications that require high-speed data exchange, such as video streaming, data acquisition, and industrial automation. The device is equipped with a USB 2.0 interface which supports full-speed operation at 12 Mbps, ensuring compatibility with a wide range of USB devices.

The CY7C68015A, a similar variant, offers additional memory options, providing users with the flexibility to select the necessary capacity for their specific applications. This part is particularly useful in scenarios that demand more users or higher data storage, making it ideal for complex USB peripherals like printers and multifunction devices. Moreover, it includes a unique capability of upgradeable firmware, ensuring that the device remains relevant and functional as technology evolves.

In contrast, the CY7C68014A stands out with its support for isochronous data transfers, making it suitable for real-time applications that require timely data delivery. This is particularly important in audio and video applications where delays can impact performance. The device incorporates advanced power management features, allowing it to operate efficiently both in low and high-power modes.

Lastly, the CY7C68016A integrates enhanced security features, positioning it as an ideal choice for applications that require data integrity and protection against unauthorized access. It supports various encryption standards and provides secure boot capabilities, making it suitable for secure environments such as financial transactions and sensitive data processing.

In summary, the CY7C68013, CY7C68015A, CY7C68014A, and CY7C68016A microcontrollers offer a versatile suite of features that cater to a wide array of USB applications. Their design emphasizes performance, flexibility, and security, making them essential components in today's rapidly evolving technology landscape. Whether in consumer electronics, industrial automation, or specialized applications, these devices provide the reliability and efficiency that engineers and developers require.
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