Cypress CY7C68016A, CY7C68015A, CY7C68014A manual Logic Block Diagram, Features CY7C68013A/14A only

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CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Logic Block Diagram

24MHz Ext. XTAL

High performance micro using standard tools with lower-power options

 

FX2LP

 

Address (16)

Data (8)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

x20

/0.5

8051 Core

 

 

I2C

 

 

 

VCC

/1.0

(8)

 

Master

 

 

 

PLL

12/24/48 MHz,

 

 

 

 

 

 

/2.0

 

 

 

 

 

 

 

four clocks/cycle

Bus

 

Additional IOs (24)

Abundant IO

 

1.5k

 

 

 

 

 

 

 

 

including two USARTS

 

 

 

Data

 

 

 

 

 

connected for

 

 

 

 

 

 

 

full-speed

 

 

 

 

 

General

 

 

 

 

 

/

 

 

ADDR (9)

 

 

 

 

 

(16)

 

 

D+

 

 

 

 

 

 

 

programmable I/F

 

 

 

 

 

GPIF

 

to ASIC/DSP or bus

 

 

USB

 

 

Address

 

 

 

 

CY

16 KB

 

 

standards such as

 

 

 

 

RDY (6)

 

 

2.0

 

 

ATAPI, EPP, etc.

D–

 

Smart

RAM

ECC

 

CTL (6)

 

XCVR

 

 

 

 

 

 

USB

 

 

 

 

 

 

Integrated

 

 

1.1/2.0

 

 

 

 

 

 

full-speed and

 

 

Engine

 

 

 

 

 

Up to 96 MBytes/s

high-speed

 

 

 

 

 

 

4 kB

8/16

 

 

 

 

 

 

burst rate

XCVR

 

 

 

 

 

 

FIFO

 

 

 

 

 

 

 

Enhanced USB core

“Soft Configuration”

FIFO and endpoint memory

Simplifies 8051 code

Easy firmware changes

(master or slave operation)

1.1 Features (CY7C68013A/14A only)

■CY7C68014A: Ideal for battery powered applications

❐Suspend current: 100 μA (typ)

■CY7C68013A: Ideal for non-battery powered applications

❐Suspend current: 300 μA (typ)

■Available in five lead-free packages with up to 40 GPIOs

❐128-pin TQFP (40 GPIOs), 100-pin TQFP (40 GPIOs), 56-pin QFN (24 GPIOs), 56-pin SSOP (24 GPIOs), and 56-pin VF- BGA (24 GPIOs)

1.2 Features (CY7C68015A/16A only)

■CY7C68016A: Ideal for battery powered applications

❐Suspend current: 100 μA (typ)

■CY7C68015A: Ideal for non-battery powered applications

❐Suspend current: 300 μA (typ)

■Available in lead-free 56-pin QFN package (26 GPIOs)

❐2 more GPIOs than CY7C68013A/14A enabling additional features in same footprint

Cypress Semiconductor Corporation’s (Cypress’s) EZ-USB FX2LP™ (CY7C68013A/14A) is a low power version of the EZ-USB FX2™ (CY7C68013), which is a highly integrated, low power USB 2.0 microcontroller. By integrating the USB 2.0 trans- ceiver, serial interface engine (SIE), enhanced 8051 microcon- troller, and a programmable peripheral interface in a single chip,

Cypress has created a cost effective solution that provides superior time-to-market advantages with low power to enable bus powered applications.

The ingenious architecture of FX2LP results in data transfer rates of over 53 Mbytes per second, the maximum allowable USB 2.0 bandwidth, while still using a low cost 8051 microcon- troller in a package as small as a 56 VFBGA (5mm x 5mm). Because it incorporates the USB 2.0 transceiver, the FX2LP is more economical, providing a smaller footprint solution than USB 2.0 SIE or external transceiver implementations. With EZ-USB FX2LP, the Cypress Smart SIE handles most of the USB 1.1 and 2.0 protocol in hardware, freeing the embedded microcontroller for application specific functions and decreasing development time to ensure USB compatibility.

The General Programmable Interface (GPIF) and Master/Slave Endpoint FIFO (8-bit or 16-bit data bus) provides an easy and glueless interface to popular interfaces such as ATA, UTOPIA, EPP, PCMCIA, and most DSP/processors.

The FX2LP draws less current than the FX2 (CY7C68013), has double the on-chip code/data RAM, and is fit, form and function compatible with the 56, 100, and 128 pin FX2.

Five packages are defined for the family: 56VFBGA, 56 SSOP, 56 QFN, 100 TQFP, and 128 TQFP.

Document #: 38-08032 Rev. *L

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Contents Features CY7C68013A/14A/15A/16A Cypress Semiconductor Corporation 198 Champion CourtFeatures CY7C68015A/16A only Logic Block DiagramFeatures CY7C68013A/14A only Applications Functional OverviewReNumeration USB Boot MethodsBus-powered Applications Interrupt SystemFIFO/GPIF Interrupt INT4 INT2 USB InterruptsPriority INT2VEC Value Source Reset and Wakeup Reset PinReset Timing Values Condition Program/Data RAMInside FX2LP Outside FX2LP Internal Code Memory, EA =Register Addresses External Code Memory, EA =Endpoint RAM Setup Data BufferEndpoint Configurations High -speed Mode Size × 64 bytes Endpoints 0 × 512 bytesExternal Fifo Interface 12.5 Default Full-Speed Alternate SettingsMaster/Slave Control Signals ArchitectureGpif Autopointer AccessECC Generation7 USB Uploads and DownloadsPart Number Conversion Table 18 I2C ControllerCompatible with Previous Generation EZ-USB FX2 Package DescriptionIfclk PE0 Pin Assignments20 CY7C68013A/14A and CY7C68015A/16A Differences PE1128 CY7C68013A/CY7C68014A Pin TqfpCY7C68013A/CY7C68014A CY7C68013A/CY7C68014A 56-pin Ssop CY7C68013A/CY7C68014A 56-pin Ssop Pin AssignmentCY7C68015A/CY7C68016A Pin QFN CY7C68013A 56-pin Vfbga Pin Assignment Top View FX2LP Pin Descriptions 128 100 56 VF Name Type Default CY7C68013A/15A Pin DescriptionsPort 56 VF Name Type Default DescriptionFX2LP Pin Descriptions FIFOADR0 IFCONFIG1..0WU2 FIFOADR1GPIFADR1 GPIFADR0PORTCCFG.0 PORTCCFG.1T1OUT Port ET0OUT T2OUTT2EX RXD1OUTINT6 GPIFADR8CTL3 FlagbFlagc CTL4Ground Register Summary FX2LP Register SummaryRegister can only be reset, it cannot be set Epie EP0CS E6CB Flowstb DPL0 = both read/write bit Operating Conditions Thermal CharacteristicsAbsolute Maximum Ratings ΘJc + θCaUSB Transceiver DC CharacteristicsAC Electrical Characteristics Program Memory Read Parameters Description Min Typ Max Unit Program Memory ReadClkout Data Memory Read Parameters Description Min Typ Max Unit Data Memory ReadCLKOUT17 Data Memory Write Parameters Description Min Max Unit Data Memory WriteStretch = Portc Strobe Feature Timings WR# Strobe Function when Portc is Accessed byGpif Synchronous Signals Gpif Synchronous Signals Timing Diagram20Slave Fifo Synchronous Read Timing Diagram20 Slave Fifo Synchronous ReadSlave Fifo Asynchronous Read Timing Diagram20 Slave Fifo Asynchronous ReadSlave Fifo Synchronous Write Timing Diagram20 Slave Fifo Synchronous WriteSlave Fifo Asynchronous Write Slave Fifo Synchronous Packet End StrobeSlave Fifo Synchronous Write Sequence and Timing Diagram Slave Fifo Asynchronous Packet End StrobeSlave Fifo Output Enable Slave Fifo Address to Flags/DataSlave Fifo Asynchronous Address FIFOADR10 to SLRD/SLWR/PKTEND Setup TimeSlave Fifo Synchronous Address RD/WR/PKTEND to FIFOADR10 Hold TimeSequence Diagram Single and Burst Synchronous Read Example10.17.2 Single and Burst Synchronous Write Sequence Diagram of a Single and Burst Asynchronous Read Slave Fifo Asynchronous Read Sequence and Timing Diagram20Sequence Diagram of a Single and Burst Asynchronous Write Slave Fifo Asynchronous Write Sequence and Timing Diagram20Ordering Information Ideal for battery powered applicationsIdeal for non-battery powered applications Development Tool KitPackage Diagrams Lead Shrunk Small Outline Package O56Lead QFN 8 x 8 mm LF56A Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A100RA Lead Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A128 PCB Layout Recommendations Vfbga 5 x 5 x 1.0 mm 0.50 Pitch, 0.30 Ball BZ56Quad Flat Package No Leads QFN Package Design Notes Cross-section of the Area Underneath the QFN PackageIssue Orig. Description of Change Date Cmcc Pyrs

CY7C68016A, CY7C68014A, CY7C68015A, CY7C68013 specifications

The Cypress CY7C68013, CY7C68015A, CY7C68014A, and CY7C68016A are part of Cypress Semiconductor's EZ-USB family of microcontrollers, known for their high performance and flexibility in USB applications. These devices are primarily used for USB interfacing and have gained popularity in various industries due to their robust features and capabilities.

One of the main features of the CY7C68013 is its Dual FIFO architecture, allowing for efficient data transfer between USB and the system memory. This feature optimizes throughput and reduces CPU overhead, making it an excellent choice for applications that require high-speed data exchange, such as video streaming, data acquisition, and industrial automation. The device is equipped with a USB 2.0 interface which supports full-speed operation at 12 Mbps, ensuring compatibility with a wide range of USB devices.

The CY7C68015A, a similar variant, offers additional memory options, providing users with the flexibility to select the necessary capacity for their specific applications. This part is particularly useful in scenarios that demand more users or higher data storage, making it ideal for complex USB peripherals like printers and multifunction devices. Moreover, it includes a unique capability of upgradeable firmware, ensuring that the device remains relevant and functional as technology evolves.

In contrast, the CY7C68014A stands out with its support for isochronous data transfers, making it suitable for real-time applications that require timely data delivery. This is particularly important in audio and video applications where delays can impact performance. The device incorporates advanced power management features, allowing it to operate efficiently both in low and high-power modes.

Lastly, the CY7C68016A integrates enhanced security features, positioning it as an ideal choice for applications that require data integrity and protection against unauthorized access. It supports various encryption standards and provides secure boot capabilities, making it suitable for secure environments such as financial transactions and sensitive data processing.

In summary, the CY7C68013, CY7C68015A, CY7C68014A, and CY7C68016A microcontrollers offer a versatile suite of features that cater to a wide array of USB applications. Their design emphasizes performance, flexibility, and security, making them essential components in today's rapidly evolving technology landscape. Whether in consumer electronics, industrial automation, or specialized applications, these devices provide the reliability and efficiency that engineers and developers require.
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