Cypress CY7C68016A manual RXD1OUT, INT6, T2EX, GPIFADR8, Slrd, Slwr, RDY2, RDY3, RDY4, RDY5, Flaga

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CY7C68013A, CY7C68014A

 

 

 

 

 

 

 

 

 

 

CY7C68015A, CY7C68016A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 11. FX2LP Pin Descriptions (continued)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

128

100

56

56

56 VF-

Name

Type

Default

Description

 

 

TQFP

TQFP

SSOP

QFN

BGA

 

 

 

 

 

 

 

112

90

 

 

 

 

 

PE4 or

IO/Z

I

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

RXD1OUT

 

(PE4)

PORTECFG.4 bit.

 

 

 

 

 

 

 

 

 

 

 

PE4 is a bidirectional IO port pin.

 

 

 

 

 

 

 

 

 

 

 

RXD1OUT is an active-HIGH output from 8051 UART1.

 

 

 

 

 

 

 

 

 

 

 

When RXD1OUT is selected and UART1 is in Mode 0,

 

 

 

 

 

 

 

 

 

 

 

this pin provides the output data for UART1 only when

 

 

 

 

 

 

 

 

 

 

 

it is in sync mode. In Modes 1, 2, and 3, this pin is HIGH.

 

113

91

 

 

 

 

 

PE5 or

IO/Z

I

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

INT6

 

(PE5)

PORTECFG.5 bit.

 

 

 

 

 

 

 

 

 

 

 

PE5 is a bidirectional IO port pin.

 

 

 

 

 

 

 

 

 

 

 

INT6 is the 8051 INT6 interrupt request input signal. The

 

 

 

 

 

 

 

 

 

 

 

INT6 pin is edge-sensitive, active HIGH.

 

114

92

 

 

 

 

 

PE6 or

IO/Z

I

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

T2EX

 

(PE6)

PORTECFG.6 bit.

 

 

 

 

 

 

 

 

 

 

 

PE6 is a bidirectional IO port pin.

 

 

 

 

 

 

 

 

 

 

 

T2EX is an active-HIGH input signal to the 8051 Timer2.

 

 

 

 

 

 

 

 

 

 

 

T2EX reloads timer 2 on its falling edge. T2EX is active

 

 

 

 

 

 

 

 

 

 

 

only if the EXEN2 bit is set in T2CON.

 

115

93

 

 

 

 

 

PE7 or

IO/Z

I

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

GPIFADR8

 

(PE7)

PORTECFG.7 bit.

 

 

 

 

 

 

 

 

 

 

 

PE7 is a bidirectional IO port pin.

 

 

 

 

 

 

 

 

 

 

 

GPIFADR8 is a GPIF address output pin.

 

 

 

 

 

 

 

 

 

 

 

4

3

8

1

1A

RDY0 or

Input

N/A

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

SLRD

 

 

following bits:

 

 

 

 

 

 

 

 

 

 

 

IFCONFIG[1..0].

 

 

 

 

 

 

 

 

 

 

 

RDY0 is a GPIF input signal.

 

 

 

 

 

 

 

 

 

 

 

SLRD is the input-only read strobe with programmable

 

 

 

 

 

 

 

 

 

 

 

polarity (FIFOPINPOLAR.3) for the slave FIFOs

 

 

 

 

 

 

 

 

 

 

 

connected to FD[7..0] or FD[15..0].

 

5

4

9

2

1B

RDY1 or

Input

N/A

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

SLWR

 

 

following bits:

 

 

 

 

 

 

 

 

 

 

 

IFCONFIG[1..0].

 

 

 

 

 

 

 

 

 

 

 

RDY1 is a GPIF input signal.

 

 

 

 

 

 

 

 

 

 

 

SLWR is the input-only write strobe with programmable

 

 

 

 

 

 

 

 

 

 

 

polarity (FIFOPINPOLAR.2) for the slave FIFOs

 

 

 

 

 

 

 

 

 

 

 

connected to FD[7..0] or FD[15..0].

 

6

5

 

 

 

 

 

RDY2

Input

N/A

RDY2 is a GPIF input signal.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

6

 

 

 

 

 

RDY3

Input

N/A

RDY3 is a GPIF input signal.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

7

 

 

 

 

 

RDY4

Input

N/A

RDY4 is a GPIF input signal.

 

 

9

8

 

 

 

 

 

RDY5

Input

N/A

RDY5 is a GPIF input signal.

 

 

 

 

 

 

 

 

 

 

 

 

69

54

36

29

7H

CTL0 or

O/Z

H

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

FLAGA

 

 

following bits:

 

 

 

 

 

 

 

 

 

 

 

IFCONFIG[1..0].

 

 

 

 

 

 

 

 

 

 

 

CTL0 is a GPIF control output.

 

 

 

 

 

 

 

 

 

 

 

FLAGA is a programmable slave-FIFO output status

 

 

 

 

 

 

 

 

 

 

 

flag signal.

 

 

 

 

 

 

 

 

 

 

 

Defaults to programmable for the FIFO selected by the

 

 

 

 

 

 

 

 

 

 

 

FIFOADR[1:0] pins.

 

Document #: 38-08032 Rev. *L

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Contents Features CY7C68013A/14A/15A/16A Cypress Semiconductor Corporation 198 Champion CourtFeatures CY7C68015A/16A only Logic Block DiagramFeatures CY7C68013A/14A only Applications Functional OverviewReNumeration USB Boot MethodsBus-powered Applications Interrupt SystemFIFO/GPIF Interrupt INT4 INT2 USB InterruptsPriority INT2VEC Value Source Reset and Wakeup Reset PinReset Timing Values Condition Program/Data RAMInside FX2LP Outside FX2LP Internal Code Memory, EA =Register Addresses External Code Memory, EA =Endpoint RAM Setup Data BufferEndpoint Configurations High -speed Mode Size × 64 bytes Endpoints 0 × 512 bytesExternal Fifo Interface 12.5 Default Full-Speed Alternate SettingsMaster/Slave Control Signals ArchitectureGpif Autopointer AccessECC Generation7 USB Uploads and DownloadsPart Number Conversion Table 18 I2C ControllerCompatible with Previous Generation EZ-USB FX2 Package DescriptionIfclk PE0 Pin Assignments20 CY7C68013A/14A and CY7C68015A/16A Differences PE1128 CY7C68013A/CY7C68014A Pin TqfpCY7C68013A/CY7C68014A CY7C68013A/CY7C68014A 56-pin Ssop CY7C68013A/CY7C68014A 56-pin Ssop Pin AssignmentCY7C68015A/CY7C68016A Pin QFN CY7C68013A 56-pin Vfbga Pin Assignment Top View FX2LP Pin Descriptions 128 100 56 VF Name Type Default CY7C68013A/15A Pin DescriptionsPort 56 VF Name Type Default DescriptionFX2LP Pin Descriptions FIFOADR0 IFCONFIG1..0WU2 FIFOADR1GPIFADR1 GPIFADR0PORTCCFG.0 PORTCCFG.1T1OUT Port ET0OUT T2OUTT2EX RXD1OUTINT6 GPIFADR8CTL3 FlagbFlagc CTL4Ground Register Summary FX2LP Register SummaryRegister can only be reset, it cannot be set Epie EP0CS E6CB Flowstb DPL0 = both read/write bit Operating Conditions Thermal CharacteristicsAbsolute Maximum Ratings ΘJc + θCaUSB Transceiver DC CharacteristicsAC Electrical Characteristics Program Memory Read Parameters Description Min Typ Max Unit Program Memory ReadClkout Data Memory Read Parameters Description Min Typ Max Unit Data Memory ReadCLKOUT17 Data Memory Write Parameters Description Min Max Unit Data Memory WriteStretch = Portc Strobe Feature Timings WR# Strobe Function when Portc is Accessed byGpif Synchronous Signals Gpif Synchronous Signals Timing Diagram20Slave Fifo Synchronous Read Timing Diagram20 Slave Fifo Synchronous ReadSlave Fifo Asynchronous Read Timing Diagram20 Slave Fifo Asynchronous ReadSlave Fifo Synchronous Write Timing Diagram20 Slave Fifo Synchronous WriteSlave Fifo Asynchronous Write Slave Fifo Synchronous Packet End StrobeSlave Fifo Synchronous Write Sequence and Timing Diagram Slave Fifo Asynchronous Packet End StrobeSlave Fifo Output Enable Slave Fifo Address to Flags/DataSlave Fifo Asynchronous Address FIFOADR10 to SLRD/SLWR/PKTEND Setup TimeSlave Fifo Synchronous Address RD/WR/PKTEND to FIFOADR10 Hold TimeSequence Diagram Single and Burst Synchronous Read Example10.17.2 Single and Burst Synchronous Write Sequence Diagram of a Single and Burst Asynchronous Read Slave Fifo Asynchronous Read Sequence and Timing Diagram20Sequence Diagram of a Single and Burst Asynchronous Write Slave Fifo Asynchronous Write Sequence and Timing Diagram20Ordering Information Ideal for battery powered applicationsIdeal for non-battery powered applications Development Tool KitPackage Diagrams Lead Shrunk Small Outline Package O56Lead QFN 8 x 8 mm LF56A Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A100RA Lead Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A128 PCB Layout Recommendations Vfbga 5 x 5 x 1.0 mm 0.50 Pitch, 0.30 Ball BZ56Quad Flat Package No Leads QFN Package Design Notes Cross-section of the Area Underneath the QFN PackageIssue Orig. Description of Change Date Cmcc Pyrs

CY7C68016A, CY7C68014A, CY7C68015A, CY7C68013 specifications

The Cypress CY7C68013, CY7C68015A, CY7C68014A, and CY7C68016A are part of Cypress Semiconductor's EZ-USB family of microcontrollers, known for their high performance and flexibility in USB applications. These devices are primarily used for USB interfacing and have gained popularity in various industries due to their robust features and capabilities.

One of the main features of the CY7C68013 is its Dual FIFO architecture, allowing for efficient data transfer between USB and the system memory. This feature optimizes throughput and reduces CPU overhead, making it an excellent choice for applications that require high-speed data exchange, such as video streaming, data acquisition, and industrial automation. The device is equipped with a USB 2.0 interface which supports full-speed operation at 12 Mbps, ensuring compatibility with a wide range of USB devices.

The CY7C68015A, a similar variant, offers additional memory options, providing users with the flexibility to select the necessary capacity for their specific applications. This part is particularly useful in scenarios that demand more users or higher data storage, making it ideal for complex USB peripherals like printers and multifunction devices. Moreover, it includes a unique capability of upgradeable firmware, ensuring that the device remains relevant and functional as technology evolves.

In contrast, the CY7C68014A stands out with its support for isochronous data transfers, making it suitable for real-time applications that require timely data delivery. This is particularly important in audio and video applications where delays can impact performance. The device incorporates advanced power management features, allowing it to operate efficiently both in low and high-power modes.

Lastly, the CY7C68016A integrates enhanced security features, positioning it as an ideal choice for applications that require data integrity and protection against unauthorized access. It supports various encryption standards and provides secure boot capabilities, making it suitable for secure environments such as financial transactions and sensitive data processing.

In summary, the CY7C68013, CY7C68015A, CY7C68014A, and CY7C68016A microcontrollers offer a versatile suite of features that cater to a wide array of USB applications. Their design emphasizes performance, flexibility, and security, making them essential components in today's rapidly evolving technology landscape. Whether in consumer electronics, industrial automation, or specialized applications, these devices provide the reliability and efficiency that engineers and developers require.
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