Cypress CY7C68016A, CY7C68013, CY7C68015A, CY7C68014A Register can only be reset, it cannot be set

Page 30

CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Table 12. FX2LP Register Summary (continued)

Hex

Size

Name

Description

b7

b6

b5

b4

b3

b2

b1

b0

Default

Access

E62B

1

ECC1B1

ECC1 Byte 1 Address

LINE7

LINE6

LINE5

LINE4

LINE3

LINE2

LINE1

LINE0

00000000

R

E62C

1

ECC1B2

ECC1 Byte 2 Address

COL5

COL4

COL3

COL2

COL1

COL0

LINE17

LINE16

00000000

R

E62D

1

ECC2B0

ECC2 Byte 0 Address

LINE15

LINE14

LINE13

LINE12

LINE11

LINE10

LINE9

LINE8

00000000

R

E62E

1

ECC2B1

ECC2 Byte 1 Address

LINE7

LINE6

LINE5

LINE4

LINE3

LINE2

LINE1

LINE0

00000000

R

E62F

1

ECC2B2

ECC2 Byte 2 Address

COL5

COL4

COL3

COL2

COL1

COL0

0

0

00000000

R

E630

1

EP2FIFOPFH[11]

Endpoint 2 / slave FIFO

DECIS

PKTSTAT

IN:PKTS[2]

IN:PKTS[1]

IN:PKTS[0]

0

PFC9

PFC8

10001000

bbbbbrbb

H.S.

 

 

Programmable Flag H

 

 

OUT:PFC12

OUT:PFC11

OUT:PFC10

 

 

 

 

 

E630

1

EP2FIFOPFH[11]

Endpoint 2 / slave FIFO

DECIS

PKTSTAT

OUT:PFC12

OUT:PFC11

OUT:PFC10

0

PFC9

IN:PKTS[2]

10001000

bbbbbrbb

F.S.

 

 

Programmable Flag H

 

 

 

 

 

 

 

OUT:PFC8

 

 

E631

1

EP2FIFOPFL[11]

Endpoint 2 / slave FIFO

PFC7

PFC6

PFC5

PFC4

PFC3

PFC2

PFC1

PFC0

00000000

RW

H.S.

 

 

Programmable Flag L

 

 

 

 

 

 

 

 

 

 

E631

1

EP2FIFOPFL[11]

Endpoint 2 / slave FIFO

IN:PKTS[1]

IN:PKTS[0]

PFC5

PFC4

PFC3

PFC2

PFC1

PFC0

00000000

RW

F.S

 

 

Programmable Flag L

OUT:PFC7

OUT:PFC6

 

 

 

 

 

 

 

 

E632

1

EP4FIFOPFH[11]

Endpoint 4 / slave FIFO

DECIS

PKTSTAT

0

IN: PKTS[1]

IN: PKTS[0]

0

0

PFC8

10001000

bbrbbrrb

H.S.

 

 

Programmable Flag H

 

 

 

OUT:PFC10

OUT:PFC9

 

 

 

 

 

E632

1

EP4FIFOPFH[11]

Endpoint 4 / slave FIFO

DECIS

PKTSTAT

0

OUT:PFC10

OUT:PFC9

0

0

PFC8

10001000

bbrbbrrb

F.S

 

 

Programmable Flag H

 

 

 

 

 

 

 

 

 

 

E633

1

EP4FIFOPFL[11]

Endpoint 4 / slave FIFO

PFC7

PFC6

PFC5

PFC4

PFC3

PFC2

PFC1

PFC0

00000000

RW

H.S.

 

 

Programmable Flag L

 

 

 

 

 

 

 

 

 

 

E633

1

EP4FIFOPFL[11]

Endpoint 4 / slave FIFO

IN: PKTS[1]

IN: PKTS[0]

PFC5

PFC4

PFC3

PFC2

PFC1

PFC0

00000000

RW

F.S

 

 

Programmable Flag L

OUT:PFC7

OUT:PFC6

 

 

 

 

 

 

 

 

E634

1

EP6FIFOPFH[11]

Endpoint 6 / slave FIFO

DECIS

PKTSTAT

IN:PKTS[2]

IN:PKTS[1]

IN:PKTS[0]

0

PFC9

PFC8

00001000

bbbbbrbb

H.S.

 

 

Programmable Flag H

 

 

OUT:PFC12

OUT:PFC11

OUT:PFC10

 

 

 

 

 

E634

1

EP6FIFOPFH[11]

Endpoint 6 / slave FIFO

DECIS

PKTSTAT

OUT:PFC12

OUT:PFC11

OUT:PFC10

0

PFC9

IN:PKTS[2]

00001000

bbbbbrbb

F.S

 

 

Programmable Flag H

 

 

 

 

 

 

 

OUT:PFC8

 

 

E635

1

EP6FIFOPFL[11]

Endpoint 6 / slave FIFO

PFC7

PFC6

PFC5

PFC4

PFC3

PFC2

PFC1

PFC0

00000000

RW

H.S.

 

 

Programmable Flag L

 

 

 

 

 

 

 

 

 

 

E635

1

EP6FIFOPFL[11]

Endpoint 6 / slave FIFO

IN:PKTS[1]

IN:PKTS[0]

PFC5

PFC4

PFC3

PFC2

PFC1

PFC0

00000000

RW

F.S

 

 

Programmable Flag L

OUT:PFC7

OUT:PFC6

 

 

 

 

 

 

 

 

E636

1

EP8FIFOPFH[11]

Endpoint 8 / slave FIFO

DECIS

PKTSTAT

0

IN: PKTS[1]

IN: PKTS[0]

0

0

PFC8

00001000

bbrbbrrb

H.S.

 

 

Programmable Flag H

 

 

 

OUT:PFC10

OUT:PFC9

 

 

 

 

 

E636

1

EP8FIFOPFH[11]

Endpoint 8 / slave FIFO

DECIS

PKTSTAT

0

OUT:PFC10

OUT:PFC9

0

0

PFC8

00001000

bbrbbrrb

F.S

 

 

Programmable Flag H

 

 

 

 

 

 

 

 

 

 

E637

1

EP8FIFOPFL[11]

Endpoint 8 / slave FIFO

PFC7

PFC6

PFC5

PFC4

PFC3

PFC2

PFC1

PFC0

00000000

RW

H.S.

 

 

Programmable Flag L

 

 

 

 

 

 

 

 

 

 

E637

1

EP8FIFOPFL[11]

Endpoint 8 / slave FIFO

IN: PKTS[1]

IN: PKTS[0]

PFC5

PFC4

PFC3

PFC2

PFC1

PFC0

00000000

RW

F.S

 

 

Programmable Flag L

OUT:PFC7

OUT:PFC6

 

 

 

 

 

 

 

 

 

8

reserved

 

 

 

 

 

 

 

 

 

 

 

E640

1

EP2ISOINPKTS

EP2 (if ISO) IN Packets

AADJ

0

0

0

0

0

INPPF1

INPPF0

00000001

brrrrrbb

 

 

 

per frame (1-3)

 

 

 

 

 

 

 

 

 

 

E641

1

EP4ISOINPKTS

EP4 (if ISO) IN Packets

AADJ

0

0

0

0

0

INPPF1

INPPF0

00000001

brrrrrrr

 

 

 

per frame (1-3)

 

 

 

 

 

 

 

 

 

 

E642

1

EP6ISOINPKTS

EP6 (if ISO) IN Packets

AADJ

0

0

0

0

0

INPPF1

INPPF0

00000001

brrrrrbb

 

 

 

per frame (1-3)

 

 

 

 

 

 

 

 

 

 

E643

1

EP8ISOINPKTS

EP8 (if ISO) IN Packets

AADJ

0

0

0

0

0

INPPF1

INPPF0

00000001

brrrrrrr

 

 

 

per frame (1-3)

 

 

 

 

 

 

 

 

 

 

E644

4

reserved

 

 

 

 

 

 

 

 

 

 

 

E648

1

INPKTEND[11]

Force IN Packet End

Skip

0

0

0

EP3

EP2

EP1

EP0

xxxxxxxx

W

E649

7

OUTPKTEND[11]

Force OUT Packet End

Skip

0

0

0

EP3

EP2

EP1

EP0

xxxxxxxx

W

 

 

INTERRUPTS

 

 

 

 

 

 

 

 

 

 

 

E650

1

EP2FIFOIE[11]

Endpoint 2 slave FIFO

0

0

0

0

EDGEPF

PF

EF

FF

00000000

RW

 

 

 

Flag Interrupt Enable

 

 

 

 

 

 

 

 

 

 

E651

1

EP2FIFOIRQ[11,12]

Endpoint 2 slave FIFO

0

0

0

0

0

PF

EF

FF

00000000

rrrrrbbb

 

 

 

Flag Interrupt Request

 

 

 

 

 

 

 

 

 

 

E652

1

EP4FIFOIE[11]

Endpoint 4 slave FIFO

0

0

0

0

EDGEPF

PF

EF

FF

00000000

RW

 

 

 

Flag Interrupt Enable

 

 

 

 

 

 

 

 

 

 

E653

1

EP4FIFOIRQ[11,12]

Endpoint 4 slave FIFO

0

0

0

0

0

PF

EF

FF

00000000

rrrrrbbb

 

 

 

Flag Interrupt Request

 

 

 

 

 

 

 

 

 

 

E654

1

EP6FIFOIE[11]

Endpoint 6 slave FIFO

0

0

0

0

EDGEPF

PF

EF

FF

00000000

RW

 

 

 

Flag Interrupt Enable

 

 

 

 

 

 

 

 

 

 

E655

1

EP6FIFOIRQ[11,12]

Endpoint 6 slave FIFO

0

0

0

0

0

PF

EF

FF

00000000

rrrrrbbb

 

 

 

Flag Interrupt Request

 

 

 

 

 

 

 

 

 

 

E656

1

EP8FIFOIE[11]

Endpoint 8 slave FIFO

0

0

0

0

EDGEPF

PF

EF

FF

00000000

RW

 

 

 

Flag Interrupt Enable

 

 

 

 

 

 

 

 

 

 

E657

1

EP8FIFOIRQ[11,12]

Endpoint 8 slave FIFO

0

0

0

0

0

PF

EF

FF

00000000

rrrrrbbb

 

 

 

Flag Interrupt Request

 

 

 

 

 

 

 

 

 

 

E658

1

IBNIE

IN-BULK-NAK Interrupt

0

0

EP8

EP6

EP4

EP2

EP1

EP0

00000000

RW

 

 

 

Enable

 

 

 

 

 

 

 

 

 

 

E659

1

IBNIRQ[12]

IN-BULK-NAK interrupt

0

0

EP8

EP6

EP4

EP2

EP1

EP0

00xxxxxx

rrbbbbbb

 

 

 

Request

 

 

 

 

 

 

 

 

 

 

E65A

1

NAKIE

Endpoint Ping-NAK / IBN

EP8

EP6

EP4

EP2

EP1

EP0

0

IBN

00000000

RW

 

 

 

Interrupt Enable

 

 

 

 

 

 

 

 

 

 

E65B

1

NAKIRQ[12]

Endpoint Ping-NAK / IBN

EP8

EP6

EP4

EP2

EP1

EP0

0

IBN

xxxxxx0x

bbbbbbrb

 

 

 

Interrupt Request

 

 

 

 

 

 

 

 

 

 

E65C

1

USBIE

USB Int Enables

0

EP0ACK

HSGRANT

URES

SUSP

SUTOK

SOF

SUDAV

00000000

RW

Note

12. The register can only be reset, it cannot be set.

Document #: 38-08032 Rev. *L

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Contents Features CY7C68013A/14A/15A/16A Cypress Semiconductor Corporation 198 Champion CourtLogic Block Diagram Features CY7C68013A/14A onlyFeatures CY7C68015A/16A only Applications Functional OverviewReNumeration USB Boot MethodsBus-powered Applications Interrupt SystemINT2 USB Interrupts Priority INT2VEC Value SourceFIFO/GPIF Interrupt INT4 Reset and Wakeup Reset PinReset Timing Values Condition Program/Data RAMInside FX2LP Outside FX2LP Internal Code Memory, EA =Register Addresses External Code Memory, EA =Endpoint RAM Setup Data BufferEndpoint Configurations High -speed Mode Size × 64 bytes Endpoints 0 × 512 bytesExternal Fifo Interface 12.5 Default Full-Speed Alternate SettingsMaster/Slave Control Signals ArchitectureGpif Autopointer AccessECC Generation7 USB Uploads and DownloadsPart Number Conversion Table 18 I2C ControllerCompatible with Previous Generation EZ-USB FX2 Package DescriptionIfclk PE0 Pin Assignments20 CY7C68013A/14A and CY7C68015A/16A Differences PE1128 CY7C68013A/CY7C68014A Pin TqfpCY7C68013A/CY7C68014A CY7C68013A/CY7C68014A 56-pin Ssop CY7C68013A/CY7C68014A 56-pin Ssop Pin AssignmentCY7C68015A/CY7C68016A Pin QFN CY7C68013A 56-pin Vfbga Pin Assignment Top View FX2LP Pin Descriptions 128 100 56 VF Name Type Default CY7C68013A/15A Pin Descriptions56 VF Name Type Default Description FX2LP Pin DescriptionsPort FIFOADR0 IFCONFIG1..0WU2 FIFOADR1GPIFADR1 GPIFADR0PORTCCFG.0 PORTCCFG.1T1OUT Port ET0OUT T2OUTT2EX RXD1OUTINT6 GPIFADR8CTL3 FlagbFlagc CTL4Ground Register Summary FX2LP Register SummaryRegister can only be reset, it cannot be set Epie EP0CS E6CB Flowstb DPL0 = both read/write bit Operating Conditions Thermal CharacteristicsAbsolute Maximum Ratings ΘJc + θCaDC Characteristics AC Electrical CharacteristicsUSB Transceiver Program Memory Read ClkoutProgram Memory Read Parameters Description Min Typ Max Unit Data Memory Read CLKOUT17Data Memory Read Parameters Description Min Typ Max Unit Data Memory Write Stretch =Data Memory Write Parameters Description Min Max Unit Portc Strobe Feature Timings WR# Strobe Function when Portc is Accessed byGpif Synchronous Signals Gpif Synchronous Signals Timing Diagram20Slave Fifo Synchronous Read Timing Diagram20 Slave Fifo Synchronous ReadSlave Fifo Asynchronous Read Timing Diagram20 Slave Fifo Asynchronous ReadSlave Fifo Synchronous Write Timing Diagram20 Slave Fifo Synchronous WriteSlave Fifo Asynchronous Write Slave Fifo Synchronous Packet End StrobeSlave Fifo Synchronous Write Sequence and Timing Diagram Slave Fifo Asynchronous Packet End StrobeSlave Fifo Output Enable Slave Fifo Address to Flags/DataSlave Fifo Asynchronous Address FIFOADR10 to SLRD/SLWR/PKTEND Setup TimeSlave Fifo Synchronous Address RD/WR/PKTEND to FIFOADR10 Hold TimeSequence Diagram Single and Burst Synchronous Read Example10.17.2 Single and Burst Synchronous Write Sequence Diagram of a Single and Burst Asynchronous Read Slave Fifo Asynchronous Read Sequence and Timing Diagram20Sequence Diagram of a Single and Burst Asynchronous Write Slave Fifo Asynchronous Write Sequence and Timing Diagram20Ordering Information Ideal for battery powered applicationsIdeal for non-battery powered applications Development Tool KitPackage Diagrams Lead Shrunk Small Outline Package O56Lead QFN 8 x 8 mm LF56A Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A100RA Lead Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A128 PCB Layout Recommendations Vfbga 5 x 5 x 1.0 mm 0.50 Pitch, 0.30 Ball BZ56Quad Flat Package No Leads QFN Package Design Notes Cross-section of the Area Underneath the QFN PackageIssue Orig. Description of Change Date Cmcc Pyrs

CY7C68016A, CY7C68014A, CY7C68015A, CY7C68013 specifications

The Cypress CY7C68013, CY7C68015A, CY7C68014A, and CY7C68016A are part of Cypress Semiconductor's EZ-USB family of microcontrollers, known for their high performance and flexibility in USB applications. These devices are primarily used for USB interfacing and have gained popularity in various industries due to their robust features and capabilities.

One of the main features of the CY7C68013 is its Dual FIFO architecture, allowing for efficient data transfer between USB and the system memory. This feature optimizes throughput and reduces CPU overhead, making it an excellent choice for applications that require high-speed data exchange, such as video streaming, data acquisition, and industrial automation. The device is equipped with a USB 2.0 interface which supports full-speed operation at 12 Mbps, ensuring compatibility with a wide range of USB devices.

The CY7C68015A, a similar variant, offers additional memory options, providing users with the flexibility to select the necessary capacity for their specific applications. This part is particularly useful in scenarios that demand more users or higher data storage, making it ideal for complex USB peripherals like printers and multifunction devices. Moreover, it includes a unique capability of upgradeable firmware, ensuring that the device remains relevant and functional as technology evolves.

In contrast, the CY7C68014A stands out with its support for isochronous data transfers, making it suitable for real-time applications that require timely data delivery. This is particularly important in audio and video applications where delays can impact performance. The device incorporates advanced power management features, allowing it to operate efficiently both in low and high-power modes.

Lastly, the CY7C68016A integrates enhanced security features, positioning it as an ideal choice for applications that require data integrity and protection against unauthorized access. It supports various encryption standards and provides secure boot capabilities, making it suitable for secure environments such as financial transactions and sensitive data processing.

In summary, the CY7C68013, CY7C68015A, CY7C68014A, and CY7C68016A microcontrollers offer a versatile suite of features that cater to a wide array of USB applications. Their design emphasizes performance, flexibility, and security, making them essential components in today's rapidly evolving technology landscape. Whether in consumer electronics, industrial automation, or specialized applications, these devices provide the reliability and efficiency that engineers and developers require.