Cypress CY7C68015A, CY7C68013, CY7C68016A, CY7C68014A manual Port E, T0OUT, T1OUT, T2OUT, RXD0OUT

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CY7C68013A, CY7C68014A

 

 

 

 

 

 

 

 

 

 

 

CY7C68015A, CY7C68016A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 11. FX2LP Pin Descriptions (continued)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

128

 

100

56

56

56 VF-

Name

Type

Default

Description

 

 

TQFP

TQFP

SSOP

QFN

BGA

 

 

 

 

 

 

 

104

 

82

54

47

6B

PD2 or

IO/Z

I

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

 

FD[10]

 

(PD2)

IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.

 

 

 

 

 

 

 

 

 

 

 

 

FD[10] is the bidirectional FIFO/GPIF data bus.

 

105

 

83

55

48

6A

PD3 or

IO/Z

I

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

 

FD[11]

 

(PD3)

IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.

 

 

 

 

 

 

 

 

 

 

 

 

FD[11] is the bidirectional FIFO/GPIF data bus.

 

121

 

95

56

49

3B

PD4 or

IO/Z

I

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

 

FD[12]

 

(PD4)

IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.

 

 

 

 

 

 

 

 

 

 

 

 

FD[12] is the bidirectional FIFO/GPIF data bus.

 

122

 

96

1

50

3A

PD5 or

IO/Z

I

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

 

FD[13]

 

(PD5)

IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.

 

 

 

 

 

 

 

 

 

 

 

 

FD[13] is the bidirectional FIFO/GPIF data bus.

 

123

 

97

2

51

3C

PD6 or

IO/Z

I

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

 

FD[14]

 

(PD6)

IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.

 

 

 

 

 

 

 

 

 

 

 

 

FD[14] is the bidirectional FIFO/GPIF data bus.

 

124

 

98

3

52

2A

PD7 or

IO/Z

I

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

 

FD[15]

 

(PD7)

IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.

 

 

 

 

 

 

 

 

 

 

 

 

FD[15] is the bidirectional FIFO/GPIF data bus.

 

Port E

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

108

 

86

 

 

 

 

 

PE0 or

IO/Z

I

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

 

T0OUT

 

(PE0)

PORTECFG.0 bit.

 

 

 

 

 

 

 

 

 

 

 

 

PE0 is a bidirectional IO port pin.

 

 

 

 

 

 

 

 

 

 

 

 

T0OUT is an active-HIGH signal from 8051

 

 

 

 

 

 

 

 

 

 

 

 

Timer-counter0. T0OUT outputs a high level for one

 

 

 

 

 

 

 

 

 

 

 

 

CLKOUT clock cycle when Timer0 overflows. If Timer0

 

 

 

 

 

 

 

 

 

 

 

 

is operated in Mode 3 (two separate timer/counters),

 

 

 

 

 

 

 

 

 

 

 

 

T0OUT is active when the low byte timer/counter

 

 

 

 

 

 

 

 

 

 

 

 

overflows.

 

109

 

87

 

 

 

 

 

PE1 or

IO/Z

I

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

 

T1OUT

 

(PE1)

PORTECFG.1 bit.

 

 

 

 

 

 

 

 

 

 

 

 

PE1 is a bidirectional IO port pin.

 

 

 

 

 

 

 

 

 

 

 

 

T1OUT is an active-HIGH signal from 8051

 

 

 

 

 

 

 

 

 

 

 

 

Timer-counter1. T1OUT outputs a high level for one

 

 

 

 

 

 

 

 

 

 

 

 

CLKOUT clock cycle when Timer1 overflows. If Timer1

 

 

 

 

 

 

 

 

 

 

 

 

is operated in Mode 3 (two separate timer/counters),

 

 

 

 

 

 

 

 

 

 

 

 

T1OUT is active when the low byte timer/counter

 

 

 

 

 

 

 

 

 

 

 

 

overflows.

 

110

 

88

 

 

 

 

 

PE2 or

IO/Z

I

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

 

T2OUT

 

(PE2)

PORTECFG.2 bit.

 

 

 

 

 

 

 

 

 

 

 

 

PE2 is a bidirectional IO port pin.

 

 

 

 

 

 

 

 

 

 

 

 

T2OUT is the active-HIGH output signal from 8051

 

 

 

 

 

 

 

 

 

 

 

 

Timer2. T2OUT is active (HIGH) for one clock cycle

 

 

 

 

 

 

 

 

 

 

 

 

when Timer/Counter 2 overflows.

 

111

 

89

 

 

 

 

 

PE3 or

IO/Z

I

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

 

RXD0OUT

 

(PE3)

PORTECFG.3 bit.

 

 

 

 

 

 

 

 

 

 

 

 

PE3 is a bidirectional IO port pin.

 

 

 

 

 

 

 

 

 

 

 

 

RXD0OUT is an active-HIGH signal from 8051 UART0.

 

 

 

 

 

 

 

 

 

 

 

 

If RXD0OUT is selected and UART0 is in Mode 0, this

 

 

 

 

 

 

 

 

 

 

 

 

pin provides the output data for UART0 only when it is

 

 

 

 

 

 

 

 

 

 

 

 

in sync mode. Otherwise it is a 1.

 

Document #: 38-08032 Rev. *L

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Contents Cypress Semiconductor Corporation 198 Champion Court Features CY7C68013A/14A/15A/16AFeatures CY7C68013A/14A only Logic Block DiagramFeatures CY7C68015A/16A only Functional Overview ApplicationsBus-powered Applications USB Boot MethodsReNumeration Interrupt SystemPriority INT2VEC Value Source INT2 USB InterruptsFIFO/GPIF Interrupt INT4 Reset Pin Reset and WakeupProgram/Data RAM Reset Timing Values ConditionInternal Code Memory, EA = Inside FX2LP Outside FX2LPExternal Code Memory, EA = Register AddressesEndpoint Configurations High -speed Mode Setup Data BufferEndpoint RAM Size × 64 bytes Endpoints 0 × 512 bytesMaster/Slave Control Signals 12.5 Default Full-Speed Alternate SettingsExternal Fifo Interface ArchitectureECC Generation7 Autopointer AccessGpif USB Uploads and DownloadsCompatible with Previous Generation EZ-USB FX2 18 I2C ControllerPart Number Conversion Table Package Description20 CY7C68013A/14A and CY7C68015A/16A Differences Pin AssignmentsIfclk PE0 PE1128 Pin Tqfp CY7C68013A/CY7C68014ACY7C68013A/CY7C68014A CY7C68013A/CY7C68014A 56-pin Ssop Pin Assignment CY7C68013A/CY7C68014A 56-pin SsopCY7C68015A/CY7C68016A Pin QFN CY7C68013A 56-pin Vfbga Pin Assignment Top View CY7C68013A/15A Pin Descriptions FX2LP Pin Descriptions 128 100 56 VF Name Type DefaultFX2LP Pin Descriptions 56 VF Name Type Default DescriptionPort WU2 IFCONFIG1..0FIFOADR0 FIFOADR1PORTCCFG.0 GPIFADR0GPIFADR1 PORTCCFG.1T0OUT Port ET1OUT T2OUTINT6 RXD1OUTT2EX GPIFADR8Flagc FlagbCTL3 CTL4Ground FX2LP Register Summary Register SummaryRegister can only be reset, it cannot be set Epie EP0CS E6CB Flowstb DPL0 = both read/write bit Absolute Maximum Ratings Thermal CharacteristicsOperating Conditions ΘJc + θCaAC Electrical Characteristics DC CharacteristicsUSB Transceiver Clkout Program Memory ReadProgram Memory Read Parameters Description Min Typ Max Unit CLKOUT17 Data Memory ReadData Memory Read Parameters Description Min Typ Max Unit Stretch = Data Memory WriteData Memory Write Parameters Description Min Max Unit WR# Strobe Function when Portc is Accessed by Portc Strobe Feature TimingsGpif Synchronous Signals Timing Diagram20 Gpif Synchronous SignalsSlave Fifo Synchronous Read Slave Fifo Synchronous Read Timing Diagram20Slave Fifo Asynchronous Read Slave Fifo Asynchronous Read Timing Diagram20Slave Fifo Synchronous Write Slave Fifo Synchronous Write Timing Diagram20Slave Fifo Synchronous Packet End Strobe Slave Fifo Asynchronous WriteSlave Fifo Asynchronous Packet End Strobe Slave Fifo Synchronous Write Sequence and Timing DiagramSlave Fifo Address to Flags/Data Slave Fifo Output EnableSlave Fifo Synchronous Address FIFOADR10 to SLRD/SLWR/PKTEND Setup TimeSlave Fifo Asynchronous Address RD/WR/PKTEND to FIFOADR10 Hold TimeSingle and Burst Synchronous Read Example Sequence Diagram10.17.2 Single and Burst Synchronous Write Slave Fifo Asynchronous Read Sequence and Timing Diagram20 Sequence Diagram of a Single and Burst Asynchronous ReadSlave Fifo Asynchronous Write Sequence and Timing Diagram20 Sequence Diagram of a Single and Burst Asynchronous WriteIdeal for non-battery powered applications Ideal for battery powered applicationsOrdering Information Development Tool KitLead Shrunk Small Outline Package O56 Package DiagramsLead QFN 8 x 8 mm LF56A Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A100RA Lead Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A128 Vfbga 5 x 5 x 1.0 mm 0.50 Pitch, 0.30 Ball BZ56 PCB Layout RecommendationsCross-section of the Area Underneath the QFN Package Quad Flat Package No Leads QFN Package Design NotesIssue Orig. Description of Change Date Pyrs Cmcc

CY7C68016A, CY7C68014A, CY7C68015A, CY7C68013 specifications

The Cypress CY7C68013, CY7C68015A, CY7C68014A, and CY7C68016A are part of Cypress Semiconductor's EZ-USB family of microcontrollers, known for their high performance and flexibility in USB applications. These devices are primarily used for USB interfacing and have gained popularity in various industries due to their robust features and capabilities.

One of the main features of the CY7C68013 is its Dual FIFO architecture, allowing for efficient data transfer between USB and the system memory. This feature optimizes throughput and reduces CPU overhead, making it an excellent choice for applications that require high-speed data exchange, such as video streaming, data acquisition, and industrial automation. The device is equipped with a USB 2.0 interface which supports full-speed operation at 12 Mbps, ensuring compatibility with a wide range of USB devices.

The CY7C68015A, a similar variant, offers additional memory options, providing users with the flexibility to select the necessary capacity for their specific applications. This part is particularly useful in scenarios that demand more users or higher data storage, making it ideal for complex USB peripherals like printers and multifunction devices. Moreover, it includes a unique capability of upgradeable firmware, ensuring that the device remains relevant and functional as technology evolves.

In contrast, the CY7C68014A stands out with its support for isochronous data transfers, making it suitable for real-time applications that require timely data delivery. This is particularly important in audio and video applications where delays can impact performance. The device incorporates advanced power management features, allowing it to operate efficiently both in low and high-power modes.

Lastly, the CY7C68016A integrates enhanced security features, positioning it as an ideal choice for applications that require data integrity and protection against unauthorized access. It supports various encryption standards and provides secure boot capabilities, making it suitable for secure environments such as financial transactions and sensitive data processing.

In summary, the CY7C68013, CY7C68015A, CY7C68014A, and CY7C68016A microcontrollers offer a versatile suite of features that cater to a wide array of USB applications. Their design emphasizes performance, flexibility, and security, making them essential components in today's rapidly evolving technology landscape. Whether in consumer electronics, industrial automation, or specialized applications, these devices provide the reliability and efficiency that engineers and developers require.
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