Cypress CY7C604XX manual ADC Electrical Specifications

Page 15

 

 

 

 

 

 

 

 

CY7C604XX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADC Electrical Specifications

 

 

 

 

 

Table 8. ADC Electrical Specifications

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

Description

Min

Typ

Max

Units

Conditions

 

Input

 

 

 

 

 

 

 

 

 

 

 

 

 

Input Voltage Range

Vss

 

1.3

V

This gives 72% of maximum code

 

 

 

 

 

 

 

 

Input Capacitance

 

 

5

pF

 

 

 

 

 

 

 

 

 

Resolution

 

8

 

Bits

 

 

 

 

 

 

 

 

 

8-Bit Sample Rate

 

23.4375

 

ksps

Data Clock set to 6 MHz. Sample Rate

 

 

 

 

 

 

 

 

= 0.001/(2^Resolution/Data clock)

 

DC Accuracy

 

 

 

 

 

 

 

 

 

 

 

 

 

DNL

-1

 

+2

LSb

For any configuration

 

 

 

 

 

 

 

 

INL

-2

 

+2

LSb

For any configuration

 

 

 

 

 

 

 

 

Offset Error

0

15

90

mV

 

 

 

 

 

 

 

 

 

Operating Current

 

275

350

μA

 

 

 

 

 

 

 

 

 

Data Clock

2.25

 

12

MHz

Source is chip’s internal main oscillator.

 

 

 

 

 

 

 

 

See AC Chip Level Specifications for

 

 

 

 

 

 

 

 

accuracy.

 

Monotonicity

 

 

 

 

Not guaranteed. See DNL

 

 

 

 

 

 

 

 

Power Supply Rejection Ratio

 

 

 

 

 

 

 

 

 

 

 

 

 

PSRR (Vdd>3.0V)

 

24

 

dB

 

 

 

 

 

 

 

 

 

PSRR (2.2 < Vdd < 3.0)

 

30

 

dB

 

 

 

 

 

 

 

 

 

PSRR (2.0 < Vdd < 2.2)

 

12

 

dB

 

 

 

 

 

 

 

 

 

PSRR (Vdd < 2.0)

 

0

 

dB

 

 

 

 

 

 

 

 

 

Gain Error

1

 

5

%FSR

For any resolution

 

 

 

 

 

 

 

 

Input Resistance

1/(500fF*D

1/(400fF*D

1/(300fF*D

Ω

Equivalent switched cap input resis-

 

 

 

 

ata-Clock)

ata-Clock)

ata-Clock)

 

tance for 8-, 9-, or 10-bit resolution.

Document Number: 001-12395 Rev *H

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Contents Low Voltage FeaturesEnCoRe V LV Block Diagram EnCoReFunctional Overview Getting Started EnCoRe V LV CoreAdditional System Resources PSoC Designer Software Subsystems Development ToolsOrganize and Connect Configure ComponentsDesigning with PSoC Designer Select ComponentsNumeric Naming Document ConventionsAcronyms Used Units of MeasurePin Part Pinout Pin ConfigurationPin Part Pinout QFN Pin No Type Name Description Vss Ground connectionP16 Digital I/O P06 Digital I/O P30 Digital I/O P32 P20 P22 P24 P26P00 Digital I/O P02 Digital I/OP15 Digital I/O, I2C SDA, SPI Miso No connection Top ViewP01 Digital I/O Vss Supply ground No connectionVdd Supply voltage No connection Vss Supply groundRegister Conventions Description Register ReferenceRegister Conventions Register Mapping TablesRegister Map Bank 0 Table User Space Name Addr 0,Hex AccessName Addr 1,Hex Access Register Map Bank 1 Table Configuration SpaceUnits of Measure Symbol Unit of Measure Electrical SpecificationsADC Electrical Specifications Operating Conditions DC Electrical CharacteristicsDC Chip Level Specifications Maximum RatingsDC General Purpose I/O Specifications High Output Voltage Vdd Port 2 or 3 Pins Current in all I/OsSink current on odd port pins for Example, P03 and P15 Input Low Voltage VddInput High Voltage Vdd Input Hysteresis Voltage DC Programming Specifications DC POR and LVD SpecificationsAC Electrical Characteristics AC Chip Level SpecificationsAC General Purpose IO Specifications AC Programming Specifications AC External Clock SpecificationsAC SPI Specifications AC SPI Specifications Symbol Description Min Typ Max UnitsWidth of SS Negated Between Transmissions AC I2C Specifications Packaging Dimensions Package DiagramPin 5 x 5 x 0.55 mm QFN 125 Package HandlingSolder Reflow Peak Temperature Thermal ImpedancesOrdering Information Document History Worldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal Information