Cypress CY7C604XX manual Maximum Ratings, Operating Conditions, DC Electrical Characteristics

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CY7C604XX

Maximum Ratings

Storage Temperature (TSTG) (5)-55oC to 125oC (Typical +25oC)

Supply Voltage Relative to Vss (Vdd)

-0.5V to +4.0V

DC Input Voltage (VIO)

Vss - 0.5V to Vdd + 0.5V

DC Voltage Applied to Tri-state (VIOZ)Vss - 0.5V to Vdd + 0.5V Maximum Current into any Port Pin (IMIO). -25mA to +50 mA

Electro Static Discharge Voltage (ESD) (6)

.................. 2000V

Latch-up Current (LU) (7)

200 mA

Operating Conditions

Ambient Temperature (TA)

0oC to 70oC

Operational Die Temperature (TJ)(8)

0oC to 85oC

DC Electrical Characteristics

DC Chip Level Specifications

Table 9 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.

Table 9. DC Chip Level Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Vdd

Supply Voltage

See table titled DC POR and LVD

1.71

3.6

V

 

 

Specifications on page 20.

 

 

 

 

IDD24

Supply Current, IMO = 24 MHz

Conditions are Vdd = 3.0V, TA = 25oC,

3.1

mA

 

 

CPU = 24 MHz

 

 

 

 

 

 

No I2C/SPI

 

 

 

 

IDD12

Supply Current, IMO = 12 MHz

Conditions are Vdd = 3.0V, TA = 25oC,

2.0

mA

 

 

CPU = 12 MHz

 

 

 

 

 

 

No I2C/SPI

 

 

 

 

IDD6

Supply Current, IMO = 6 MHz

Conditions are Vdd = 3.0V, TA = 25oC,

1.5

mA

 

 

CPU = 6 MHz

 

 

 

 

 

 

No I2C/SPI

 

 

 

 

ISB0

Deep Sleep Current

Vdd = 3.0V, TA = 25oC, IO regulator

0.1

μA

 

 

turned off

 

 

 

 

ISB1

Standby Current with POR, LVD, and

Vdd = 3.0V, TA = 25oC, IO regulator

1.5

μA

 

Sleep Timer

turned off

 

 

 

 

Notes

5.Higher storage temperatures reduce data retention time. Recommended storage temperature is +25°C ± 25°C. Extended duration storage temperatures above 85°C degrade reliability.

6.Human Body Model ESD.

7.According to JESD78 standard.

8.The temperature rise from ambient to junction is package specific. See on page 27. The user must limit the power consumption to comply with this requirement.

Document Number: 001-12395 Rev *H

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Contents Features EnCoRe V LV Block DiagramEnCoRe Low VoltageEnCoRe V LV Core Functional Overview Getting StartedAdditional System Resources Development Tools PSoC Designer Software SubsystemsConfigure Components Designing with PSoC DesignerSelect Components Organize and ConnectDocument Conventions Acronyms UsedUnits of Measure Numeric NamingPin Configuration Pin Part PinoutVss Ground connection Pin Part Pinout QFN Pin No Type Name DescriptionP16 Digital I/O P30 Digital I/O P32 P20 P22 P24 P26 P00 Digital I/OP02 Digital I/O P06 Digital I/OTop View P15 Digital I/O, I2C SDA, SPI Miso No connectionVss Supply ground No connection Vdd Supply voltage No connectionVss Supply ground P01 Digital I/ORegister Reference Register ConventionsRegister Mapping Tables Register Conventions DescriptionName Addr 0,Hex Access Register Map Bank 0 Table User SpaceRegister Map Bank 1 Table Configuration Space Name Addr 1,Hex AccessElectrical Specifications Units of Measure Symbol Unit of MeasureADC Electrical Specifications DC Electrical Characteristics DC Chip Level SpecificationsMaximum Ratings Operating ConditionsDC General Purpose I/O Specifications Vdd Port 2 or 3 Pins Current in all I/Os High Output VoltageInput Low Voltage Vdd Sink current on odd port pins for Example, P03 and P15Input High Voltage Vdd Input Hysteresis Voltage DC POR and LVD Specifications DC Programming SpecificationsAC Chip Level Specifications AC Electrical CharacteristicsAC General Purpose IO Specifications AC External Clock Specifications AC Programming SpecificationsAC SPI Specifications Symbol Description Min Typ Max Units AC SPI SpecificationsWidth of SS Negated Between Transmissions AC I2C Specifications Package Diagram Packaging DimensionsPin 5 x 5 x 0.55 mm QFN Package Handling 125Thermal Impedances Solder Reflow Peak TemperatureOrdering Information Document History Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions